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ASTM F1211-89(2001)

(Specification)

Standard Specification for Semiconductor Device Passivation Opening Layouts (Withdrawn 2007)

Standard Specification for Semiconductor Device Passivation Opening Layouts (Withdrawn 2007)

SCOPE
1.1 This specification covers standard semiconductor device passivation opening layouts for various tape automated bonding interconnection technologies.
1.2 This specification establishes the nominal passivation opening dimensions, nominal passivation, opening spacing, nominal corner passivation opening offset, minimum scribe guard and minimum die size for the most common input/ output counts within each technology.
1.3 This specification is extendable to other interconnection technologies if the passivation opening and spacing are adjusted in such a way that the progression is not modified.
1.4 The values stated in SI units are to be regarded as the standard. The values given in parentheses are for information only.
WITHDRAWN RATIONALE
This specification covers standard semiconductor device passivation opening layouts for various tape automated bonding interconnection technologies.
Formerly under the jurisdiction of Committee F01 on Electronics and Subcommittee F01.07 on Wire Bonding, Flip Chip, and Tape Automated Bonding, this specification was withdrawn in July 2007 in accordance with section 10.6.3.1 of the Regulations Governing ASTM Technical Committees, which requires that standards shall be updated by the end of the eighth year since the last approval date.

General Information

Status
Withdrawn
Publication Date
31-Dec-2000
Withdrawal Date
26-Aug-2007
ICS
31.080.01 - Semiconductor devices in general
Technical Committee
F01 - Electronics
Current Stage
Ref Project

Relations

Replaces
ASTM F1211-89(1994)e1 - Standard Specification for Semiconductor Device Passivation Opening Layouts
Effective Date
01-Jan-2001

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ASTM F1211-89(2001) - Standard Specification for Semiconductor Device Passivation Opening Layouts (Withdrawn 2007)ASTM F1211-89(2001) - Standard Specification for Semiconductor Device Passivation Opening Layouts (Withdrawn 2007)
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ASTM F1211-89(2001) - Standard Specification for Semiconductor Device Passivation Opening Layouts (Withdrawn 2007)
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NOTICE: This standard has either been superseded and replaced by a new version or withdrawn.
Contact ASTM International (www.astm.org) for the latest information
Designation: F 1211 – 89 (Reapproved 2001)
Standard Specification for
1
Semiconductor Device Passivation Opening Layouts
This standard is issued under the fixed designation F 1211; the number immediately following the designation indicates the year of
original adoption or, in the case of revision, the year of last revision. A number in parentheses indicates the year of last reapproval. A
superscript epsilon (e) indicates an editorial change since the last revision or reapproval.
1. Scope 2.1.6 passivation opening size—The minimum othagonal
dimensions of the passivation opening for the particular
1.1 This specification covers standard semiconductor device
technology herein used as the nominal passivation opening
passivation opening layouts for various tape automated bond-
size.
ing interconnection technologies.
2.1.7 passivation opening space—The minimum space be-
1.2 This specification established the nominal passivation
tween adjacent passivation openings for the particular technol-
opening dimensions, nominal passivation, opening spacing,
ogy herein used as the nominal passivation opening spacing.
nominal corner passivation opening offset, minimum scribe
2.1.8 progression—The dimension as measured from a
guard and minimum die size for the most common input/output
reference point on one passivation opening to the same
counts within each technology.
reference point on the adjacent passivation opening.
1.3 This specification is extendable to other interconnection
2.1.9 technology—The minimum passivation opening pro-
technologies if the passivation opening and spacing are ad-
gression allowable for a specific interconnection method.
justed in such a way that the progression is not modified.
1.4 The values stated in SI units are to be regarded as the
3. Classification
standard. The values given in parentheses are for information
3.1 The passivation opening layouts are separated into four
only.
technology types where:
2. Terminology Type I = 220 µm technology (220 µm = 8.7 mils)
Type II = 185 µm technology (185 µm = 7.3 mils)
2.1 Definitions:
Type III = 150 µm technology (150 µm = 5.9 mils)
2.1.1 corner offset—The orthogonal distance between the
Type IV = 100 µm technology (100 µm = 3.9 mils)
corner passivation opening on adjacent sides of the die where
a corner passivation opening is indentified as the end passiva-
4. Dimensions, Mass, and Permissible Variations
tion opening on a die side.
4.1 The primary unit of measure is micrometres (µm) (1
2.1.2 lead count—The number of passivation openings
micrometre = 1 micron) and the secondary unit of measure is
available on a fully populated die layout.
mils (1/1000 of an in.), where 1 mil (0.001 in.) = 25.4 µm.
2.1.3 minimum die edge guard—The minimum distance
4.2 Fig. 1 shows the generic dimension measurement for
between the die edge and the passivation opening nearest to the
each defined dimension.
die edge herein used to establish the minimum die size.
4.3 The lead count independent dimensions are summarized
2.1.4 minimum die size—The minimum die size is calcu-
in Table 1 for all technologies.
lated by the following equation:
4.4 The specific standard layouts are listed in Tables 2-5 for
minimum die size5~~lead count/4!~p.o. size 1 p.o. space!!
Type I,Type II,Type III andType IVtechnologies respectively.
2 p.o. space1~2 ~corner offset 1 p.o. size
4.5 Progression—Any variations must be noncumulative.
1 die edge guard!!
4.6 Lead Count—All passivation openings as specified in
2.1.5 passivation opening—The unpassivated area within
this specification must be included in the design whether they
the device metal bonding pad area.
are or are not connected internally.
5. Keywords
1
This specification is under the jurisdiction of ASTM Committee F01 on
Electronics and is the direct responsibility of Subcommittee F01.07 on Wire
5.1 opening layouts; passivation; semiconductor devices
Bonding, Flip Chip, and Tape Automated Bonding.
Current edition approved Feb. 24, 1989. Published April 1989.
Copyright © ASTM International, 100 Barr Harbor Drive, PO Box C700, West Conshohocken, PA 19428-2959, United States.
1

---------------------- Page: 1 ----------------------
F 1211 – 89 (2001)
TABLE 3 Specific Dimensions for the Type II (185 µm)
Technology for Each Lead Count
Passivation Passivation Minimum
Corner Minimum
Lead Count Opening Opening Die Edge
Offset, µm Die Size,
n Size, µm Space, µm Guard, µm
(mil) µm (mil)
(mil) (mil) (mil)
28 80 (3.14) 105 (4.13) 188 (7.40) 125 (4.92) 2.0 (78)
32 80 (3.14) 105 (4.13) 188 (7.40) 125 (4.92) 2.2 (86)
40 80 (3.14) 105 (4.13) 188 (7.40) 125 (4.92) 2.6 (100)
44 80 (3.14) 105 (4.13) 188 (7.40) 125 (4.92) 2.8 (107)
68 80 (3.14) 105 (4.13) 188 (7.40) 125 (4.92) 3.9 (151)
84 80 (3.14) 105 (4.13) 188 (7.40) 125 (4.92) 4.6 (180)
100 80 (3.14) 105 (4.13) 188 (7.40) 125 (4.92) 5.4 (209)
132 80 (3.14) 105
...

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Semiconductor devices are permanently damaged by reactor spectrum neutrons. The effect of such damage on the performance of an electronic component can be determined by measuring the component electrical characteristics before and after exposure to fast neutrons in the neutron fluence range of interest. The resulting data can be utilized in the design of electronic circuits that are tolerant of the degradation exhibited by that component.
This guide provides a method by which the exposure of silicon and gallium arsenide semiconductor devices to neutron irradiation may be performed in a manner that is repeatable and which will allow comparison to be made of data taken at different facilities.
For semiconductors other than silicon and gallium arsenide, this guide provides a method that can improve consistency in the measurements and assurance that data from various facilities can be compared on the same equivalence fluence scale when the applicable validated 1-MeV damage functions are codified in National standards. In the absence of a validated 1-MeV damage function, the non-ionizing energy loss (NIEL) as a function incident neutron energy, normalized to the NIEL at 1 MeV, may be used as an approximation. See Practice E 722 for a description of the method.
SCOPE
1.1 This guide strictly applies only to the exposure of unbiased silicon (SI) or gallium arsenide (GaAs) semiconductor components (integrated circuits, transistors, and diodes) to neutron radiation from a nuclear reactor source to determine the permanent damage in the components. Validated 1-MeV damage functions codified in National Standards are not currently available for other semiconductor materials.
1.2 Elements of this guide with the deviations noted may also be applicable to the exposure of semiconductors comprised of other materials except that validated 1-MeV damage functions codified in National standards are not currently available.
1.3 Only the conditions of exposure are addressed in this guide. The effects of radiation on the test sample should be determined using appropriate electrical test methods.
1.4 This guide addresses those issues and concerns pertaining to irradiations with reactor spectrum neutrons.
1.5 System and subsystem exposures and test methods are not included in this guide.
1.6 This guide is applicable to irradiations conducted with the reactor operating in either the pulsed or steady-state mode. The range of interest for neutron fluence in displacement damage semiconductor testing range from approximately 109  to 1016  n/cm 2.
1.7 This guide does not address neutron-induced single or multiple neutron event effects or transient annealing.
1.8 This guide provides an alternative to Test Method 1017.3, Neutron Displacement Testing, a component of MIL-STD-883 and MIL-STD-750. The Department of Defense has restricted use of these MIL-STDs to programs existing in 1995 and earlier.
This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

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