CEN/TR 17602-60-02:2021
(Main)Space product assurance - Techniques for radiation effects mitigation in ASICs and FPGAs handbook
Space product assurance - Techniques for radiation effects mitigation in ASICs and FPGAs handbook
This handbook provides a compilation of different techniques that can be used to mitigate the adverse effects of radiation in integrated circuits (ICs), with almost exclusive attention to Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs) to be used in space, and excluding other ICs like power devices, MMIC or sensors.
The target users of this handbook are developers and users of ICs which are meant to be used in a radiation environment. Following a bottom-up order, the techniques are presented according to the different stages of an IC development flow where they can be applied. Therefore, users of this handbook can be IC engineers involved in the selection, use or development of IC manufacturing processes, IC layouts and ASIC standard cell libraries, analogue and digital circuit designs, FPGAs, embedded memories, embedded software and the immediate electronic system (printed circuit board) containing the IC that can experience the radiation effects.
In addition, this handbook contains an overview of the space radiation environment and its effects in semiconductor devices, a section on how to validate the good implementation and effectiveness of the mitigation techniques, and a special section providing some general guidelines to help with the selection of the most adequate mitigation techniques including some examples of typical space project scenarios.
The information given in this ECSS Handbook is provided only as guidelines and for reference, and not to be used as requirements. ECSS Standards provide requirements that can be made applicable, while, ECSS Handbooks provide guidelines.
Raumfahrtproduktsicherung - Handbuch zu Minderungsmethoden von Strahlungseffekten auf ASICs und FPGAs
Ingénierie spatiale - Guide sur les techniques de durcissement des ASICs et FPGAs vis-à-vis des effets des radiations
Zagotavljanje kakovosti proizvodov v vesoljski tehniki - Priročnik za tehnike blaženja učinkov sevanja na vezja ASIC in FPGA
Ta priročnik podaja različne tehnike, ki jih je mogoče uporabiti za ublažitev škodljivih učinkov sevanja v integriranih vezjih (IC), s skoraj izključnim poudarkom na integriranih vezjih za določen namen (ASIC) in terensko programirljivih logičnih vezjih (FPGA), ki se uporabljajo v vesolju, pri čemer so izključena druga integrirana vezja, kot so omrežne naprave, mikrovalovna integrirana vezja (MMIC) ali senzorji.
Ciljni uporabniki tega priročnika so razvijalci in uporabniki integriranih vezij, namenjenih za uporabo v okolju s sevanjem. Tehnike so predstavljene v vrstnem redu od spodaj navzgor glede na različne stopnje poteka razvoja integriranih vezij, za katere jih je mogoče uporabiti. Uporabniki tega priročnika so torej lahko inženirji integriranih vezij, ki so vključeni v izbiro, uporabo ali razvoj postopkov izdelave integriranih vezij, postavitev integriranih vezij in knjižnic standardnih celic ASIC, načrtov analognih in digitalnih vezij, terensko programirljivih logičnih vezij, vgrajenih pomnilnikov, vgrajene programske opreme ter neposrednega elektronskega sistema (tiskanega vezja), ki vsebuje integrirano vezje, na katere lahko vpliva sevanje.
Ta priročnik vsebuje tudi pregled sevanja v vesoljskem okolju in njegovih učinkov v polprevodniških napravah, razdelek o tem, kako preveriti ustrezno izvajanje in učinkovitost tehnik blaženja, ter poseben razdelek, ki vsebuje nekaj splošnih smernic za pomoč pri izbiri najustreznejše tehnike blaženja, vključno z nekaterimi primeri običajnih scenarijev vesoljskih projektov.
Informacije v tem priročniku ECSS so zgolj smernice in reference ter se ne uporabljajo kot zahteve. Standardi ECSS podajajo zahteve, ki jih je mogoče uporabiti, medtem ko priročniki ECSS podajajo smernice.
General Information
Standards Content (Sample)
SLOVENSKI STANDARD
01-februar-2022
Zagotavljanje kakovosti proizvodov v vesoljski tehniki - Priročnik za tehnike
blaženja učinkov sevanja na vezja ASIC in FPGA
Space product assurance - Techniques for radiation effects mitigation in ASICs and
FPGAs handbook
Raumfahrtproduktsicherung - Handbuch zu Minderungsmethoden von
Strahlungseffekten auf ASICs und FPGAs
Ingénierie spatiale - Guide sur les techniques de durcissement des ASICs et FPGAs vis-
à-vis des effets des radiations
Ta slovenski standard je istoveten z: CEN/TR 17602-60-02:2021
ICS:
03.120.99 Drugi standardi v zvezi s Other standards related to
kakovostjo quality
49.140 Vesoljski sistemi in operacije Space systems and
operations
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.
TECHNICAL REPORT CEN/TR 17602-60-02
RAPPORT TECHNIQUE
TECHNISCHER BERICHT
December 2021
ICS 49.140
English version
Space product assurance - Techniques for radiation effects
mitigation in ASICs and FPGAs handbook
Ingénierie spatiale - Guide sur les techniques de Raumfahrtproduktsicherung - Handbuch zu
durcissement des ASICs et FPGAs vis-à-vis des effets Minderungsmethoden von Strahlungseffekten auf
des radiations ASICs und FPGAs
This Technical Report was approved by CEN on 22 November 2021. It has been drawn up by the Technical Committee
CEN/CLC/JTC 5.
CEN and CENELEC members are the national standards bodies and national electrotechnical committees of Austria, Belgium,
Bulgaria, Croatia, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy,
Latvia, Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Republic of North Macedonia, Romania, Serbia,
Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and United Kingdom.
CEN-CENELEC Management Centre:
Rue de la Science 23, B-1040 Brussels
© 2021 CEN/CENELEC All rights of exploitation in any form and by any means Ref. No. CEN/TR 17602-60-02:2021 E
reserved worldwide for CEN national Members and for
CENELEC Members.
Table of contents
European Foreword . 14
1 Scope . 15
2 References . 16
3 Terms, definitions and abbreviated terms . 17
3.1 Terms from other documents . 17
3.2 Terms specific to the present document . 17
3.3 Abbreviated terms. 19
4 Radiation environment and integrated circuits . 25
4.1 Overview . 25
4.2 Radiation environment in space . 25
4.3 Radiation Effects in ICs . 26
4.3.1 Overview . 26
4.3.2 Cumulative effects. 26
4.3.3 Single Event Effects (SEEs) . 27
4.3.3.1 Overview. 27
4.3.3.2 Non-destructive SEE . 28
4.3.3.3 Destructive SEE . 29
4.3.3.4 Summary . 30
5 Choosing a device hardening strategy . 31
5.1 The optimal strategy . 31
5.2 How to use this handbook . 32
6 Technology selection and process level mitigation . 35
6.1 Overview . 35
6.2 Mitigation techniques . 36
6.2.1 Epitaxial layers . 36
6.2.2 Silicon On Insulator . 37
6.2.3 Triple wells . 40
6.2.4 Buried layers . 42
6.2.5 Dry thermal oxidation . 43
6.2.6 Implantation into oxides . 45
6.3 Technology scaling and radiation effects . 46
7 Layout . 49
7.1 Overview . 49
7.2 Mitigation techniques . 50
7.2.1 Ringed or Enclosed Layout Transistor . 50
7.2.2 Contacts and guard rings . 52
7.2.3 Dummy transistors . 55
7.2.4 Transistors Gate W/L ratio sizing . 57
8 Analogue circuits . 58
8.1 Overview . 58
Mitigation techniques . 59
8.2
8.2.1 Node Separation and Inter-digitation . 59
8.2.2 Analogue redundancy (averaging) . 63
8.2.3 Resistive decoupling . 64
8.2.4 Filtering . 67
8.2.5 Modifications in bandwidth, gain, operating speed, and current
drive . 68
8.2.6 Reduction of window of vulnerability . 71
8.2.7 Reduction of high impedance nodes . 75
8.2.8 Differential design . 77
8.2.9 Dual path hardening . 80
9 Embedded memories . 85
9.1 Overview . 85
9.2 Mitigation techniques . 86
9.2.1 Hardening of individual memory cells . 86
9.2.1.1 Overview. 86
9.2.1.2 Resistive hardening . 86
9.2.1.3 Capacitive hardening . 87
9.2.1.4 IBM hardened memory cell . 89
9.2.1.5 HIT hardened memory cell . 91
9.2.1.6 DICE hardened memory cell . 92
9.2.1.7 NASA-Whitaker hardened memory cell . 94
9.2.1.8 NASA-Liu hardened memory cell . 95
9.2.2 Bit-interleaving in memory arrays . 97
9.2.3 Data scrubbing . 99
9.3 Comparison between hardened memory cells . 100
10 Radiation-hardened ASIC libraries . 101
10.1 Introduction . 101
10.2 IMEC Design Against Radiation Effects (DARE) library . 102
10.3 CERN 0,25 µm radiation hardened library . 103
10.4 BAE 0,15 µm radiation hardened library . 103
10.5 Ramon Chips 0,18 µm and 0,13 µm radiation hardened libraries . 103
10.6 Cobham (former Aeroflex) 600, 250, 130 and 90 nm radiation hardened
libraries . 104
10.7 Microchip Atmel MH1RT 0,35 µm and ATC18RHA 0,18 µm CMOS and
ATMX150RHA 0,15 µm SOI CMOS radiation hardened libraries . 104
10.8 ATK 0,35 µm radiation hardened cell library . 105
10.9 ST Microelectronics C65SPACE 65 nm radiation hardened library . 105
10.10 RedCat Devices radiation hardened libraries . 105
11 Digital circuits . 106
11.1 Overview . 106
11.2 Mitigation techniques . 107
11.2.1 Spatial redundancy . 107
11.2.1.1 Description of the concept . 107
11.2.1.2 Duplex architectures . 108
11.2.1.3 Triple Modular Redundancy architectures . 109
11.2.1.3.1 General . 109
11.2.1.3.2 Basic TMR . 109
11.2.1.3.3 Full TMR . 110
11.2.2 Temporal redundancy . 113
11.2.2.1 Description of the concept . 113
11.2.2.1.1 Overview . 113
11.2.2.1.2 Triple Temporal Redundancy combined with spatial redundancy 114
11.2.2.1.3 Minimal level sensitive latch . 115
11.2.3 Fail-safe, deadlock-free finite state machines . 117
11.2.4 Selective use of logic cells, clock and reset lines hardening . 121
12 System on a chip . 123
12.1 Overview . 123
12.2 Mitigation techniques . 124
12.2.1 Error Correcting Codes . 124
12.2.1.1 Introduction to multiple options . 124
12.2.1.1.1 General . 124
12.2.1.1.3 Cyclic Redundancy Check . 126
12.2.1.1.4 BCH codes . 127
12.2.1.1.5 Hamming codes . 127
12.2.1.1.6 SEC-DED codes . 128
12.2.1.1.7 Reed-Solomon codes . 128
12.2.1.1.8 Arithmetic codes . 128
12.2.1.1.9 Low Density Parity Codes . 129
12.2.2 Mitigation for Memory Blocks . 130
12.2.3 Filtering SET pulses in data paths . 131
12.2.4 Watchdog timers . 133
12.2.5 TMR in mixed-signal circuits . 135
13 Field programmable gate arrays . 138
13.1 Overview . 138
13.2 Mitigation techniques .
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