prEN IEC 61189-3-720:2025

Test methods for electrical materials, printed boards and other interconnection structures and assemblies - Part 3-720: Test methods for interconnection structures (circuit boards) - Transmission loss test method for high frequency multilayer circuit boards

Prüfverfahren für Elektromaterialien, Leiterplatten und andere Verbindungsstrukturen und Baugruppen – Teil 3-720: Prüfverfahren für Verbindungsstrukturen (Leiterplatten) – Prüfverfahren für Übertragungsverluste bei Hochfrequenz-Mehrschichtleiterplatten

Preskusne metode za električne materiale, tiskana vezja ter druge povezovalne strukture in sestave - 3-720. del: Preskusne metode za povezovalne strukture (tiskana vezja) - Preskusna metoda za določanje prenosnih izgub pri visokofrekvenčnih večplastnih tiskanih vezjih

General Information

• Status: Not Published
• Publication Date: 18-Jul-2027
• ICS: 31.180 - Printed circuits and boards
• Technical Committee: CLC/SR 91 - Electronics assembly technology
• Current Stage: 4060 - Enquiry results established and sent to TC, SR, BTTF - Enquiry
• Start Date: 20-Mar-2026
• Completion Date: 20-Mar-2026
• Ref Project: oSIST prEN IEC 61189-3-720:2026 - Test methods for electrical materials, printed boards and other interconnection structures and assemblies - Part 3-720: Test methods for interconnection structures (circuit boards) - Transmission loss test method for high frequency multilayer circuit boards

Overview

The prEN IEC 61189-3-720:2025 standard, developed by the CLC and scheduled for publication in 2026, defines test methods for electrical materials, printed boards, and other interconnection assemblies. Specifically, Part 3-720 addresses the transmission loss test method for high frequency multilayer circuit boards (CBs). This standard focuses on measuring the internal transmission circuit's performance in multilayer PCBs operating at frequencies up to 50 GHz.

The testing technique utilizes S-parameter measurements combined with a specialized test specimen design employing the Via In Pad Plated Over (VIPPO) structure. VIPPO technology, along with back-drilling, is introduced to enhance measurement precision by minimizing signal degradation due to parasitic effects such as stubs.

Key Topics

• S-Parameter Test Method:
  The standard uses S-parameters to evaluate signal loss and integrity in multilayer circuit boards, describing the relationship between input and output signals at different ports in the frequency domain. Particularly, S21 (transmission coefficient) is used to quantify transmission loss.

• VIPPO Structure:
  The VIPPO structure involves plated vias that are filled and capped on the PCB surface to create solderable pads while eliminating the negative effects of via stubs on high-frequency signals. This technique improves signal integrity and measurement accuracy for high-frequency testing.

• Back-Drilling Technique:
  Integrated with VIPPO, back-drilling removes unused via stubs that cause signal reflections and losses, further optimizing the transmission path for accurate characterization of multilayer PCBs.

• Apparatus and Setup:
  Test apparatus includes a Vector Network Analyzer (VNA) capable of operating up to 50 GHz, an appropriate test fixture to connect the device under test (DUT) to the VNA, and test specimens designed to replicate real high-frequency conditions. The VNA's capabilities in dynamic range, bandwidth, and port configuration are critical for reliable measurements.

• Test Specimen Design:
  The standard specifies the use of test specimens featuring single-ended or differential transmission lines with precise dimensions and impedance matching. The specimens incorporate VIPPO vias and utilize back-drilling to reduce parasitic effects. The test setup controls parameters such as board thickness, dielectric constant (Dk), and dielectric loss tangent (Df) to simulate actual application environments.

• Measurement Procedures and Reporting:
  Detailed procedures for preparing specimens, performing transmission loss measurements, and reporting results are outlined to ensure consistent and reproducible data across test labs and manufacturers.

Applications

prEN IEC 61189-3-720:2025 is highly relevant for organizations involved in:

• High-Frequency PCB Design and Manufacturing:
  Engineers designing multilayer PCBs for RF, microwave, and high-speed digital applications benefit from this standard by verifying transmission losses accurately to meet signal integrity requirements.

• Quality Control and Testing Laboratories:
  Test labs use this method to validate PCB transmission performance and support compliance with industry standards.

• Telecommunications and Aerospace Industries:
  High-frequency circuit boards used in communication infrastructure, radar, and avionics require precise characterization of signal transmission to maintain performance and reliability.

• Research and Development:
  Material scientists and PCB fabricators utilize these test methods to evaluate new materials and interconnection structures tailored for ultra-high frequency applications.

Related Standards

• IEEE P370:
  This standard covers fixture design and data quality metrics for interconnect testing up to 50 GHz, complementing prEN IEC 61189-3-720 by specifying measurement fixture requirements.

• IEC 61189-3 Series:
  The broader IEC 61189-3 family addresses various test methods for electrical and interconnection materials and printed boards, establishing a comprehensive framework for PCB testing.

• IEC Electropedia & ISO Online Browsing Platform:
  These resources provide terminology and definitions critical for standardized communication across electrical and electronic testing disciplines.

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By implementing the prEN IEC 61189-3-720 test method, stakeholders can achieve enhanced accuracy in transmission loss measurements for multilayer high-frequency circuit boards, ultimately ensuring better signal integrity and performance in advanced electronic systems.

Standards Content (Sample)

SLOVENSKI STANDARD
01-februar-2026
Preskusne metode za električne materiale, tiskana vezja ter druge povezovalne
strukture in sestave - 3-720. del: Preskusne metode za povezovalne strukture
(tiskana vezja) - Preskusna metoda za določanje prenosnih izgub pri
visokofrekvenčnih večplastnih tiskanih vezjih
Test methods for electrical materials, printed boards and other interconnection structures
and assemblies - Part 3-720: Test methods for interconnection structures (circuit boards)
- Transmission loss test method for high frequency multilayer circuit boards
Ta slovenski standard je istoveten z: prEN IEC 61189-3-720:2025
ICS:
31.180 Tiskana vezja (TIV) in tiskane Printed circuits and boards
plošče
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

91/2081/CDV
COMMITTEE DRAFT FOR VOTE (CDV)

PROJECT NUMBER:
IEC 61189-3-720 ED1
DATE OF CIRCULATION: CLOSING DATE FOR VOTING:
2025-12-26 2026-03-20
SUPERSEDES DOCUMENTS:
91/2013/CD, 91/2056/CC
IEC TC 91 : ELECTRONICS ASSEMBLY TECHNOLOGY
SECRETARIAT: SECRETARY:
Japan Mr Osamu IKEDA
OF INTEREST TO THE FOLLOWING COMMITTEES: HORIZONTAL FUNCTION(S):

ASPECTS CONCERNED:
SUBMITTED FOR CENELEC PARALLEL VOTING NOT SUBMITTED FOR CENELEC PARALLEL VOTING
Attention IEC-CENELEC parallel voting
The attention of IEC National Committees, members of
CENELEC, is drawn to the fact that this Committee Draft for
Vote (CDV) is submitted for parallel voting.
The CENELEC members are invited to vote through the
CENELEC online voting system.
This document is still under study and subject to change. It should not be used for reference purposes.
Recipients of this document are invited to submit, with their comments, notification of any relevant patent rights of which t hey
are aware and to provide supporting documentation.
Recipients of this document are invited to submit, with their comments, notification of any relevant “In Some Countries”
clauses to be included should this proposal proceed. Recipients are reminded that the CDV stage is the final stage for
submitting ISC clauses. (SEE AC/22/2007 OR NEW GUIDANCE DOC).

TITLE:
Test methods for electrical materials, printed boards and other interconnection structures and
assemblies - Part 3-720: Test methods for interconnection structures (circuit boards) - Transmission
loss test method for high frequency multilayer circuit boards

PROPOSED STABILITY DATE: 2030
NOTE FROM TC/SC OFFICERS:
Approved in WG.
electronic file, to make a copy and to print out the content for the sole purpose of preparing National Committee positions.
You may not copy or "mirror" the file or printed version of the document, or any part of it, for any other purpose without
permission in writing from IEC.

IEC CDV 61189-3-720 ED1 © IEC 2025
1 CONTENTS
3 FOREWORD . 2
4 INTRODUCTION . 4
5 1 Scope . 5
6 2 Normative references . 5
7 3 Terms and definitions . 5
8 4 Apparatus . 7
9 4.1 Signal loss test system . 7
10 4.2 VNA (Vector Network Analyzer) . 7
11 4.3 Test fixture . 7
12 5 test specimen . Error! Bookmark not defined.
13 6 Procedures . 9
14 6.1 Preparing the test specimen . 9
15 6.2 Test procedure . 9
16 7 Report. 10
17 Annex A (informative) Reducing parasitic effects by using VIPPO structure . 11
18 Annex B (informative) test specimen design for verifying of transmission characteristics . 13
19 Annex C (informative) IEEE P370 de-embedding method with 2x thru standard . 15
20 Annex D (informative) Comparison of S parameter characteristics according to via structure16
21 Bibliography . 17
23 Figure 1 – Schematic diagram of VIPPO structure (side view) . 6
24 Figure 2 – S Parameter block diagram for 2-port RF device . 6
25 Figure 3 - Concept for 2 port signal loss test system . 7
26 Figure 4 - Structure of test specimen with VIPPO design . 9
27 Figure A.1 – Two type of via pad structure for test specimen . 11
28 Figure A.2 – Two type of VIPPO structure for test specimen. 12
29 Figure B.1 – Photograph of test specimens in 3 design types . 13
30 Figure B.2 – Structure of launch pad in 2 design types . 13
31 Figure B.3 - Various type of test specimen design . 14
32 Figure C.1 – De embedding structure with 2X thru . 15
33 Figure D.1 - Comparison graph of S parameter characteristics according to via structure . 16
35 Table A.1 – Parasitic effects and signal integrity of dog bone and VIPPO structures …………11
IEC CDV 61189-3-720 ED1 © IEC 2025
37 INTERNATIONAL ELECTROTECHNICAL COMMISSION
38 ____________
39 TEST METHODS FOR ELECTRICAL MATERIALS, PRINTED BOARDS AND OTHER
40 INTERCONNECTION STRUCTURES AND ASSEMBLIES –
42 PART 3-720: TEST METHODS FOR INTERCONNECTION STRUCTURES (CIRCUIT
43 BOARDS) –
45 TRANSMISSION LOSS TEST METHOD FOR HIGH FREQUENCY MULTILAYER
46 CIRCUIT BOARDS
49 FOREWORD
50 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising all national
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79 IEC shall not be held responsible for identifying any or all such patent rights.
80 IEC 6XXXX has been prepared by subcommittee XX: TITLE, of IEC technical committee XX: TITLE. It
81 is […an International Standard, a Technical Specification: specify document type…].
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IEC CDV 61189-3-720 ED1 © IEC 2025
89 The committee has decided that the contents of this document will remain unchanged until the stability
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IEC CDV 61189-3-720 ED1 © IEC 2025
97 INTRODUCTION
98 The International Electrotechnical Commission (IEC) draws attention to the fact that it is claimed that
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IEC CDV 61189-3-720 ED1 © IEC 2025
110 TEST METHODS FOR ELECTRICAL MATERIALS, PRINTED BOARDS AND OTHER
111 INTERCONNECTION STRUCTURES AND ASSEMBLIES –
113 PART 3-720: TEST METHODS FOR INTERCONNECTION STRUCTURES (CIRCUIT
114 BOARDS) –
116 TRANSMISSION LOSS TEST METHOD FOR HIGH FREQUENCY MULTILAYER
117 CIRCUIT BOARDS
120 Scope
121 This International Standard specifies the S Parameter test method for the internal transmission circuit
122 of a multilayer CB(Circuit Board) for high frequency up to 50 GHz. The transmission loss test method
123 that applies the VIPPO structure to the CB surface contributes to improving the signal loss measurement
124 precision and signal integrity of the internal transmission circuit of the high frequency CB. And use of
125 back-drilling with Via In Pad Plated Over(VIPPO) structure can eliminate influence of stubs on signal
126 transmission.
128 Normative references
129 The following documents are referred to in the text in such a way that some or all of their content
130 constitutes requirements of this document. For dated references, only the edition cited applies. For
131 undated references, the latest edition of the referenced document (including any amendments) applies.
132 IEEE P370, A Fixture Design and Data Quality Metric Standard for Interconnects up to 50 GHz
133 Terms and definitions
134 For the purposes of this document, the following terms and definitions apply.
135 ISO and IEC maintain terminology databases for use in standardization at the following addresses:
136 • IEC Electropedia: available at https://www.electropedia.org/
137 • ISO Online browsing platform: available at https://www.iso.org/obp
138 3.1
139 Via in pad plated over
140 VIPPO
141 plated hole that has been filled with conductive or non-conductive material, capped, and plated over,
142 thereby forming a solderable surface pad (see Figure 1).
IEC CDV 61189-3-720 ED1 © IEC 2025
145 Key
146 1 plated via
147 2 filled via with conductive or non-conductive material
148 3 over plated cap
149 NOTE Figure 1 shows the side view of a CB formed with VIPPO structure.
150 Figure 1 – Schematic diagram of VIPPO structure (side view)
151 3.2
152 S Parameter
153 ratio of output voltage to input voltage in frequency domain, The “S Parameters” describe the
154 relationship between the incident and reflected waves at each port. For example, S21 means the ratio
155 of the transmitted output voltage at port 2 to the input voltage at port 1. In other words, it is a value that
156 indicates how much power input into port 1 is output through port 2. Where S11 means the ratio of the
157 reflected voltage at port 1 to the input voltage at port 1. Where S12 means the ratio of the transmitted
158 output voltage at port 1 to the input voltage at port 2. Where S22 means the ratio of the reflected voltage
159 at port 2 to the input voltage at port 2. (see Figure 2).
160 NOTE  Figure 2 shows the S Parameter block diagram for forward trnsmission of a 2-port RF device
161 Figure 2 - S Parameter block diagram for 2 port RF device
oSIST prEN IEC 61189
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