WG 13 - TC 91/WG 13

IEC TR 63051:2017(E) describes the main functional requirements for an HDLMath language and compares existing HDLMath languages from the viewpoint of designers. It is intended to accelerate the standardization of a mathematical algorithm design language and to help establish a new and good system modeling and verification environment.

IEC/TR 62856:2013 describes features for existing design languages, as well as for enhancing and newly developing design languages belonging to the defined design processes of System on a chip (SoC) which ranges from system level design, SoC design implementation and verification, IP block creation and analog block design down to interface data preparation for manufacturing. Thirty-three design languages have been chosen and each feature of their latest version as of March 2011 is reflected in this report:
UML, Esterel, Rosetta, SystemC, SystemC-AMS, IBIS, CITI, TouchStone, BSDL, System Verilog, VHDL, Verilog HDL, UPF, CPF, e language, PSL, FSDB, SDC, DEF, Open Access, SDF, GDS II, OASIS, STIL, WGL, Verilog-A, Verilog-AMS, SPICE, VHDL-AMS, LEF, Liberty, CDL and IP-XACT.

IEC 62531:2012(E) defines the property specification language (PSL), which formally describes electronic system behavior. This standard specifies the syntax and semantics for PSL and also clarifies how PSL interfaces with various standard electronic system design languages. This second edition cancels and replaces the first edition, published in 2007, and constitutes a technical revision.

IEC 61523-1:2012(E) focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity. This second edition cancels and replaces the first edition, published in 2001, and constitutes a technical revision.

IEC 62530:2011(E) Provides a unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL. This publication has the status of a double logo IEEE/IEC standard.

IEC 61691-1-1:2011(E) Revises and enhances the VHDL language reference manual (LRM) by including a standard C language interface specification. The VHDL language was defined for use in the design and documentation of electronics systems. It is revised to incorporate capabilities that improve the language's usefulness for its intended purpose as well as extend it to address design verification methodologies that have developed in industry. These new design and verification capabilities are required to ensure VHDL remains relevant and valuable for use in electronic systems design and verification. Incorporation of previously separate, but related standards, simplifies the maintenance of the specifications. This publication has the status of a double logo IEEE/IEC standard.

IEC 61691-7:2009(E) defines SystemC®1 as an ANSI standard C++ class library for system and hardware design. The specific purpose is to provide a precise and complete defination of the System C class library so that a System C implementation can be developed.

IEC 61691-6:2009(E) Defines IEC 61691-6/IEEE Std 1076.1 language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. The language, also informally known as VHDLAMS, is built on the IEC 61691-1-1/IEEE 1076 (VHDL) language and extends it to provide capabilities of writing and simulating analog and mixed-signal models.

The Standard Delay Format (SDF)is an existing OVI standard for the representation and interpretation of timing data for use at any stage of the electronic design process.The ASCII data in the SDF le is represented in a tool and language independent way and includes path delays,timing constraint values,inter-connect delays and high level technology parameters. This standard is published with a double logo IEC-IEEE. standard.