ISO/IEC 15776:2001

VME64bus - Specification

The VMEbus specification defines an interfacing system used to interconnect microprocessors, data storage and peripheral control devices in a closely-coupled hardware configuration. Its objectives include allowing communication between devices on the VMEbus without disturbing the internal activities of other devices on the VMEbus, allowing a broad range of design latitude so that the designer can optimize cost and/or performance without affecting system compatibility, and providing a system where performance is primarily device-limited rather than system-interface-limited.  Note that this publication is available not in paper form but as a CD-ROM.

General Information

• Status: Published
• Publication Date: 20-Dec-2001
• ICS: 01 - GENERALITIES. TERMINOLOGY. STANDARDIZATION. DOCUMENTATION
• ICS: 35.160 - Microprocessor systems
• Technical Committee: ISO/IEC JTC 1/SC 25 - Interconnection of information technology equipment
• Current Stage: PPUB - Publication issued
• Start Date: 31-Jan-2001
• Completion Date: 21-Dec-2001

Standards Content (Sample)

INTERNATIONAL ISO/IEC
STANDARD
First edition
2001-12
VME64bus – Specification
Reference number
INTERNATIONAL ISO/IEC
STANDARD 15776
First edition
2001-12
VME64bus – Specification
© ISO/IEC 2001
All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form or by any
means, electronic or mechanical, including photocopying and microfilm, without permission in writing from the publisher.
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CONTENTS
FOREWORD .8
INTRODUCTION.9
1 General.13
1.1 Scope and object .13
1.2 Normative references.13
1.3 VMEbus interface system elements.14
1.4 VMEbus specification diagrams.20
1.5 Specification terminology .22
1.6 Protocol specification .24
1.7 System examples and explanations.25
2 Data transfer bus.25
2.1 Introduction.25
2.2 Data-transfer-bus lines.27
2.3 DTB modules – Basic description .38
2.4 Typical operation.64
2.5 Data-transfer-bus acquisition .73
2.6 DTB timing rules and observations .75
3 Data transfer bus arbitration.120
3.1 Bus arbitration philosophy.120
3.2 Arbitration bus lines.122
3.3 Functional modules .124
3.4 Typical operation.132
3.5 Race conditions between master requests and arbiter grants.141
4 Priority interrupt bus.141
4.1 Introduction.141
4.2 Priority interrupt bus lines.144
4.3 Priority interrupt bus modules – Basic description .146
4.4 Typical operation.159
4.5 Race conditions.165
4.6 Priority interrupt bus timing rules and observations .166
5 Utility bus .183
5.1 Introduction.183
5.2 Utility bus signal lines. .183
5.3 Utility bus modules .183
5.4 System initialization and diagnostics.186
5.5 Power and ground pins .190
5.6 Reserved line .191
5.7 Auto slot ID.191
5.8 Auto system controller.198
6 Electrical specifications .199
6.1 Introduction.199
6.2 Power distribution.200
6.3 Electrical signal characteristics .201
6.4 Bus driving and receiving requirements .202

15776 © ISO/IEC:2001(E) – 3 –
6.5 Backplane signal line interconnections .206
6.6 User defined signals.210
6.7 Signal line drivers and terminations .210
7 Mechanical specifications.212
7.1 Introduction.212
7.2 VMEbus boards.213
7.3 Front panels .217
7.4 Backplanes.220
7.5 Assembly of VMEbus subracks.222
7.6 Conduction cooled VMEbus systems.223
7.7 VMEbus backplane connectors and VMEbus board connectors .223
Annex A (normative) Glossary of VMEbus terms .245
Annex B (normative) VMEbus Connector/Pin description .251
Annex C (normative) Manufacturer’s board identification.255
Rule index.257
Figure 1 – System elements.15
Figure 2 – Functional modules and buses.21
Figure 3 – Signal timing notation .25
Figure 4 – Data transfer bus functional block diagram.28
Figure 5 – Block diagram – Master.39
Figure 6 – Block diagram – Slave.41
Figure 7 – Block diagram – Bus timer .43
Figure 8 – Block diagram – Location monitor.44
Figure 9 – Four ways in which 32 bits of data might be stored in memory.53
Figure 10 – Four ways in which 16 bits of data might be stored in memory.54
Figure 11 – Block diagram – Configuration ROM / Control & Status registers.59
Figure 12 – Example of a non-multiplexed address, single-byte read cycle .66
Figure 13 – Example of multiplexed address double-byte write cycle.67
Figure 14 – Example of non-multiplexed address quad-byte write cycle.69
Figure 15 – Example of an eight-byte block read cycle.70
Figure 16 – Data transfer bus master exchange sequence .74
Figure 17 – Address broadcast timing – All cycles.94
Figure 18 – A16, A24, A32 master, responding slave, and location monitor.95
Figure 19 – Master, slave, and location monitor – A16, A24 and A32 address broadcast timing .96
Figure 20 – Master, slave, and location monitor A16, A24, and A32 address broadcast timing .97
Figure 21 – Master, slave and location monitor – A64, A40, and ADOH address
broadcast timing .98
Figure 22 – Master, slave, and location monitor data transfer timing.99
Figure 23 – Master, slave, and location monitor data transfer timing.101

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Figure 24 – Master, slave and location monitor data transfer timing A40 multiplexed
quad byte read, A40BLT multiplexed quad byte block read, MBLT eight byte block read .103
Figure 25 – Master, slave and location monitor data transfer timing.105
Figure 26 – Master, slave and location monitor data transfer timing.107
Figure 27 – Master, slave and location monitor data transfer timing A40 multiplexed
quad byte write, A40BLT multiplexed quad byte block write, MBLT eight byte block write .109
Figure 28 – Master, slave and location monitor data transfer timing single-byte RMW cycles .111
Figure 29 – Master, slave and location monitor data transfer timing double-byte
RMW cycles, quad-byte RMW cycles.112
Figure 30 – Address strobe inter-cycle timing .113
Figure 31 – Data strobe inter-cycle timing.113
Figure 32 – Data strobe inter-cycle timing.114
Figure 33 – Master, slave and bus timer data transfer timing timed-out cycle .114
Figure 34 – Master DTB control transfer timing.115
Figure 35 – Master and slave data transfer timing master responding to RETRY* line .116
Figure 36 – Master and slave data transfer timing master ignoring RETRY* line .117
Figure 37 – A40, MD32 read-modify-write.118
Figure 38 – Rescinding DTACK timing.119
Figure 39 – Arbitration functional block diagram .121
Figure 40 – Illustration of the daisy chain bus grant lines.123
Figure 41 – Block diagram – Arbiter .127
Figure 42 – Block diagram – Requester.130
Figure 43 – Arbitration flow diagram two requesters, two request levels .134
Figure 44 – Arbitration sequence diagram two requesters, two request levels .136
Figure 45 – Arbitration flow diagram two requesters, same request level.137
Figure 46 – Arbitration seque
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