ISO/IEC 14575:2000

Information technology - Microprocessor systems - Heterogeneous InterConnect (HIC) (Low-Cost, Low-Latency Scalable Serial Interconnect for Parallel System Construction)

The construction of high-performance systems with parallel communications, parallel processing, and/or parallel I/O demands a fast, low-cost, low-latency interconnect. It must be fast and low-latency, otherwise it will be the limiting factor in system performance; and it must be low-cost, or it will dominate the system cost. This standard has been developed to complement recent technical developments of highly integrated, low-power interconnect technology implemented in high-volume commodity VLSI processes, and to exploit the simplifications in encodings and protocols resulting from the use of relatively reliable media over relatively short distances.

General Information

• Status: Published
• Publication Date: 10-Jul-2000
• ICS: 01 - GENERALITIES. TERMINOLOGY. STANDARDIZATION. DOCUMENTATION
• ICS: 35.160 - Microprocessor systems
• Technical Committee: ISO/IEC JTC 1/SC 25 - Interconnection of information technology equipment
• Current Stage: PPUB - Publication issued
• Start Date: 30-Nov-1998
• Completion Date: 11-Jul-2000

Standards Content (Sample)

INTERNATIONAL ISO/IEC
STANDARD
IEEE
Std 1355
First edition
2000-07
Information Technology –
Microprocessor Systems – Heterogeneous
InterConnect (HIC) (Low-Cost, Low-Latency
Scalable Serial Interconnect for
Parallel System Construction)
Reference number
IEEE Std 1355, 1998 Edition
Abstract: Enabling the construction of high-performance, scalable, modular, parallel systems
with low system integration cost is discussed. Complementary use of physical connectors and
cables, electrical properties, and logical protocols for point-to-point serial scalable
interconnect, operating at speeds of 10 200 Mb/s and at 1 Gb/s in copper and optic
technologies, is described.
Keywords: flow control, encoding schemes, OMI/HIC, packet routing, parallelism, point-to-
point serial scalable interconnect, protocols, routing fabric, serial links, serialization, silicon
integration, switch chip, transaction layer, wormhole routing.

––––––––––––
The Institute of Electrical and Electronics Engineers, Inc.
345 East 47th Street, New York, NY 10017-2394, USA
Copyright © 1998 by the Institute of Electrical and Electronics Engineers, Inc.
All rights reserved. First published in 1998.
ISBN 2-8318-5321-4
No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without
the prior written permission of the publisher.

INTERNATIONAL ISO/IEC
STANDARD
IEEE
Std 1355
First edition
2000-07
Information Technology –
Microprocessor Systems – Heterogeneous
InterConnect (HIC) (Low-Cost, Low-Latency
Scalable Serial Interconnect for
Parallel System Construction)
Sponsor
Bus Architecture Standards Committee
of the IEEE Computer Society
PRICE CODE
XB
For price, see current catalogue

– 2 – ISO/IEC 14575:2000(E)
IEEE Std 1355, 1998 Edition
CONTENTS
Page
FOREWORD . 8
INTRODUCTION .9
Clause
1 Scope and object . 15
2 Normative references . 15
3 Definitions. 17
3.1 General. 17
3.2 Glossary . 17
4 Physical media and logical layers . 23
4.1 Physical media. 23
4.2 Logical layers. 24
4.3 Interaction of layers. 27
4.4 Implementations defined in this International Standard . 29
5 DS-SE and DS-DE . 31
5.1 General. 31
5.2 DS-SE: physical medium . 32
5.3 DS-SE signal level . 32
5.4 DS-DE: physical medium. 38
5.5 DS-DE signal level . 44
5.6 DS-SE and DS-DE character level. 46
5.7 DS-SE and DS-DE exchange level . 48
6 TS-FO-02 fiber optic link . 51
6.1 Physical medium . 51
6.2 Signal level . 53
6.3 TS-FO character level . 55
6.4 TS-FO exchange level. 57
7 HS-SE-10.62
7.1 HS-SE physical medium . 62
7.2 HS-SE signal level . 66
7.3 HS character level (8B/12B code). 69
7.4 HS exchange level . 86
8 HS-FO-10 fiber optic link . 94
8.1 Physical medium . 94
8.2 Signal level . 97
8.3 Character level and exchange level . 99
9 Common packet level. 99
9.1 General discussion. 99
9.2 Packet format . 99
9.3 Networks and routing . 100
9.4 Error detection, recovery, and reporting. 101
10 Conformance criteria. 101
10.1 Conformance statements . 101
10.2 Definition of subsets. 101
Copyright © 1998 IEEE. All rights reserved.

IEEE Std 1355, 1998 Edition
Annex A (normative) DS-DE connector specification . 103
Annex B (normative) HS-SE connector specification . 110
Annex C (normative) TS-FO and HS-FO connector specifications . 116
Annex D (informative) Rationale . 128
Annex E (informative) Switch chips, switches, and fabrics . 132
Annex F (informative) Use of the transaction layer – Asynchronous transfer mode (ATM)
example . 134
Annex G (informative) Error handling . 145
Annex H (informative) Flow control calculations . 146
Annex I (informative) Synchronized channel communications . 149
Annex J (informative) Example DS-SE driver circuit . 152
Annex K (informative) DS-DE optional power supply recommendation . 154
Annex L (informative) DS-DE fixed connector PCB recommendation . 155
Annex M (informative) DS-DE cable (10 core) recommendation. 156
Annex N (informative) DS-DE multiway connector housing recommendation. 157
Annex O (informative) HS-SE fixed connector PCB recommendation. 158
Annex P (informative) HS-SE cable recommendation . 159
Annex Q (informative) HS-SE connector multiway housing recommendation. 160
Annex R (informative) TS/HS-FO connector PCB and front panel cut-out recommendation . 161
Annex S (informative) TS/HS-FO fiber cable recommendation. 162
Figure 1 – Protocol stack between nodes . 23
Figure 2 – Exchange layer . 26
Figure 3 – Protocol stack diagram showing interaction of layers . 28
Figure 4 – Defined implementation of physical and logical layers. 30
Figure 5 – DS-SE link signal propagation . 33
Figure 6 – DS-SE timing reference model . 35
Figure 7 – DS-SE link timings . 36
Figure 8 – DS-SE link signal encoding . 37
Figure 9 – DS-DE cable assembly twist example. 40
Figure 10 – DE-DE extension adapter . 40
Figure 11 – DS-DE fixed connector external view. 41
Figure 12 – Multiple power connectors . 43
Figure 13 – DS-SE/DS character encoding. 46
Figure 14 – DS-SE/DS-DE parity coverage. 47
Figure 15 – DS link states. 49
Figure 16 – DS link start-up and reset. 50
Figure 17 – TS-FO cable fibers/plugs wiring. 52
Figure 18 – TS-FO extension adapter . 52
Figure 19 – TS-FO fixed adaptor, external view and ferrule allocation. 53
Figure 20 – TS-FO reference list. 54
Figure 21 – TS-FO link states . 58
Figure 22 – TS link start-up and reset . 59
Copyright © 1998 IEEE. All rights reserved.

– 4 – ISO/IEC 14575:2000(E)
IEEE Std 1355, 1998 Edition
Figure 23 – TS-FO packet encoding. 61
Figure 24 – Single braid and double braid link cables . 64
Figure 25 – HS-SE cable pins/connectors wiring . 65
Figure 26 – HS-SE extension adapter . 65
Figure 27 – HS-SE fixed connector external view . 65
Figure 28 – Input and output buffer electrical model . 67
Figure 29 – Exchange level interconnection between two nodes . 87
Figure 30 – Transmitter state machine controller-start-up. 88
Figure 31 – Transmitter state machine controller-functional. 89
Figure 32 – Transmitter state machine controller-shutdown. 89
Figure 33 – Receiver state machine controller. 90
Figure 34 – Exchange for start-up, functional and shutdown. 91
Figure 35 – Exchange for bidirectional start-up . 92
Figure 36 – HS-FO cable fibers/plugs wiring . 95
Figure 37 – HS-FO extension adapter . 96
Figure 38 – HS-FO fixed adapter, external view and ferrule allocation . 96
Figure 39 – HS-FO reference link . 98
Figure A.1 – DS-DE fixed connector front view. 105
Figure A.2 – DS-DE fixed connector side view. 106
Figure A.3 – DS-DE fixed connector top view . 106
Figure A.4 – DS-DE connector latch. 107
Figure A.5 – DS-DE free connector front view . 108
Figure A.6 – DS-DE free connector side view.
...