IEC TS 62878-2-1:2015

Device embedded substrate - Part 2-1: Guidelines - General description of technology

IEC TS 62878-2-1:2015 describes the basics of device embedding substrate. It is applicable to device embedded substrates fabricated by use of organic base material, which include for example active or passive devices, discrete components formed in the fabrication process of electronic wiring board, and sheet formed components.

Substrat avec appareil(s) intégré(s) - Partie 2-1: Directives - Description générale de la technologie

L'IEC TS 62878-2-1:2015 décrit les bases des substrats d'intégration d'appareil. Il est applicable aux substrats avec appareil(s) intégré(s) fabriqués à partir de matériaux de base organiques, y compris par exemple les appareils actifs ou passifs, les composants discrets formés lors du processus de fabrication d'une carte de câblage électronique, ainsi que les composants de feuilles minces.

General Information

• Status: Published
• Publication Date: 29-Mar-2015
• ICS: 31.180 - Printed circuits and boards
• ICS: 31.190 - Electronic component assemblies
• Technical Committee: TC 91 - Electronics assembly technology
• Drafting Committee: WG 6 - TC 91/WG 6
• Current Stage: PPUB - Publication issued
• Start Date: 30-Mar-2015
• Completion Date: 15-Mar-2015

Standards Content (Sample)

IEC TS 62878-2-1 ®
Edition 1.0 2015-03
TECHNICAL
SPECIFICATION
SPECIFICATION
TECHNIQUE
colour
inside
Device embedded substrate –
Part 2-1: Guidelines – General description of technology

Substrat avec appareil(s) intégré(s) –
Partie 2-1: Directives – Description générale de la technologie

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IEC TS 62878-2-1 ®
Edition 1.0 2015-03
TECHNICAL
SPECIFICATION
SPECIFICATION
TECHNIQUE
colour
inside
Device embedded substrate –
Part 2-1: Guidelines – General description of technology

Substrat avec appareil(s) intégré(s) –

Partie 2-1: Directives – Description générale de la technologie

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.180; 31.190 ISBN 978-2-8322-2434-2

– 2 – IEC TS 62878-2-1:2015 © IEC 2015
CONTENTS
FOREWORD . 4
INTRODUCTION . 6
1 Scope . 7
2 Normative references. 7
3 Terms, definitions and abbreviations . 7
3.1 Terms and definitions . 7
3.2 Abbreviations . 7
4 Technology of device embedded substrate . 7
4.1 Basic structures . 7
4.2 Technology of device embedded substrate . 9
4.3 Structures of device embedded substrates and terms used in this specification
........................................................................................................................... 12
5 Jisso mounting and interconnection . 13
5.1 General . 13
5.2 Interconnections and structures of device embedded substrate . 15
5.3 Device embedding by conventional process . 17
5.4 Device embedding using vias . 19
6 Naming of each section . 22
6.1 General . 22
6.2 General definition of top and bottom surfaces . 22
6.3 Naming of layers and interconnection position . 24
6.4 Definitions of insulation layer thickness, conductor gap and connection
distance between terminal and conductor . 27
6.4.1 General . 27
6.4.2 Insulation layer thickness, conductor gap and electrode/conductor gap in
pad connection . 27
6.4.3 Insulation layer thickness, conductor gap and electrode/conductor gap in
a via connection . 28
6.5 Additional information . 28
6.5.1 Additional information for the insulation layer . 28
6.5.2 Additional information for conductor gap and electrode/conductor gap . 29
Bibliography . 30

Figure 1 – Examples of device embedded substrate . 8
Figure 2 – Completed device embedded substrate (pad connection) . 9
Figure 3 – Completed device embedded substrate (via connection) . 9
Figure 4 – Structure of a pad connection type substrate on a passive device embedded
ceramics base . 10
Figure 5 – Structure of a device embedded substrate using a ceramic board as the base
(via connection type) . 10
Figure 6 – Entire structure of device embedded substrate . 15
Figure 7 – Base (typical structure) . 16
Figure 8 – Base (cavity structure) . 16
Figure 9 – Base (insulator) . 16

– 3 – IEC TS 62878-2-1:2015 © IEC 2015

Figure 10 – Base (Conductive carrier – metal plate). 16
Figure 11 – Passive device embedded ceramic board used as a base . 17
Figure 12 – Ceramic board used as base (ceramic) . 17
Figure 13 – Wire bonding connection and embedding of active device bare die . 17
Figure 14 – Soldering connection and embedding of active device . 18
Figure 15 – Soldering connection of square type passive device . 18
Figure 16 – Conductive resin connection and embedding of active device . 18
Figure 17 – Conductive resin connection and embedding of square type passive device . 19
Figure 18 – Soldering connection into through hole and embedding of passive device . 19
Figure 19 – Connection by copper plating after embedding of active device . 19
Figure 20 – Connection by copper plating after embedding of square type passive
device . 20
Figure 21 – Conductive paste connection after embedding of active device package . 20
Figure 22 – Conductive paste connection after embedding of square type passive device
chip 20
Figure 23 – Device embedded substrate for device embedding in multi-layers . 21
Figure 24 – Embedding of devices over multiple layers . 21
Figure 25 – Resin base substrate . 21
Figure 26 – Conductor and metal sheet/copper foil as base substrate . 22
Figure 27 – Device embedded substrate using passive device embedded ceramic
substrates as base substrate – Second type . 22
Figure 28 – Definition of top and bottom surfaces . 23
Figure 29 – Definition of top and bottom surfaces (mounting of a mother board) . 23
Figure 30 – Names of layers in pad connection . 24
Figure 31 – Additional information concerning the interconnection position . 25
Figure 32 – Names of layers in via connection [I] . 25
Figure 33 – Names of layers in via connection [II] . 26
Figure 34 – Names of layers in via connection [III] . 26
Figure 35 – Definition of insulating layer thickness and conductor gap in pad connection
Figure 36 – Definition of electrode gap in via connection . 28
Figure 37 – Additional illustration of insulating layer thickness . 29
Figure 38 – Additional illustration for conductor gap and electrode/connector gap . 29

Table 1 – Classification of device embedding . 11
Table 2 – Formed embedded device into the substrate . 12
Table 3 – Embedded device structure and fabrication process . 13
Table 4 – Jisso mounting and interconnection of device embedded substrate . 14
Table 5 – Names of layers of device embedded board . 27

– 4 – IEC TS 62878-2-1:2015 © IEC 2015
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
DEVICE EMBEDDED SUBSTRATE –
Part 2-1: Guidelines – General description of technology

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international
co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and in
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preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent
rights. IEC shall not be held responsible for identifying any or all such patent rights.
The main task of IEC technical committees is to prepare International Standards. In exceptional
circumstances, a technical committee may propose the publication of a Technical Specification
when
• the required support cannot be obtained for the publication of an International Standard,
despite repeated efforts, or
• the subject is still under technical development or where, for any other reason, there is the
future but no immediate possibility of an agreement on an International Standard.
Technical Specifications are subject to review within three years of publication to decide
whether they can be transformed into International Standards.
IEC TS 62878-2-1, which is a Technical Specification, has been prepared by IEC technical
committee 91: Electronics assembly technology.

– 5 – IEC TS 62878-2-1:2015 © IEC 2015

The text of this Technical Specification is based on the following documents:
Enquiry draft Report on voting
91/1142/DTS 91/1163A/RVC
Full information on the voting for the approval of this Technical Specification can be found in the
report on voting indicated in the above table.
A list of all parts in the IEC 62878 series, published under the general title Device embedded
substrate, can be found on the IEC website.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
The committee has decided that the contents of this publication will remain unchanged until the
stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to
the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct understanding
of its contents. Users should therefore print this document using a colour printer.

– 6 – IEC TS 62878-2-1:2015 © IEC 2015
INTRODUCTION
This part of IEC 62878 provides guidance with respect to device embedded substrate, fabricated
by embedding discrete active and passive electronic devices into one or multiple inner layers of
a substrate with electric connections by means of vias, conductor plating, conductive paste, and
printing. Within the IEC 62878 series,
• IEC 62878-1-1 specifies the test methods,
• IEC TS 62878-2-1 gives a general description of the technology,
• IEC TS 62878-2-3 provides guidance on design, and
• IEC TS 62878-2-4 specifies the test element groups.
The device embedded substrate may be used as a substrate to mount SMDs to form electronic
circuits, as conductor and insulator layers may be formed after embedding electronic devices.
The purpose of the IEC 62878 series is to achieve a common understanding with respect to
structures, test methods, design and fabrication processes and the use of the device embedded
substrate in industry.
– 7 – IEC TS 62878-2-1:2015 © IEC 2015

DEVICE EMBEDDED SUBSTRATE –
Part 2-1: Guidelines – General description of technology

1 Scope
This part of IEC 62878 describes the basics of device embedding substrate.
This part of IEC 62878 is applicable to device embedded substrates fabricated by use of
organic base material, which include for example active or passive devices, discrete
components formed in the fabrication process of electronic wiring board, and sheet formed
components.
The IEC 62878 series neither applies to the re-distribution layer (RDL) nor to the electronic
modules defined as an M-type business model in IEC 62421.
2 Normative references
The following documents, in whole or in part, are normatively referenced in this document and
are indispensable for its application. For dated references, only the edition cited applies. For
undated references, the latest edition of the referenced document (including any amendments)
applies.
IEC 60194, Printed board design, manufacture and assembly – Terms and definitions
IEC 61189 (all parts), Test methods for electrical materials, printed boards and other
interconnection structures and assemblies
3 Terms, definitions and abbreviations
3.1 Terms and definitions
For the purposes of this document, the terms and definitions given in IEC 60194 apply.
3.2 Abbreviations
BGA ball grid array
I/O in/out
IPD integrated passive device
LGA land grid array
LTCC low temperature co-fired ceramic
MEMS micro electro mechanical systems
PoP package on package
QFN quad flat no-lead package
QFP quad flat package
SMD surface mount device
SOJ small outline J-leaded package
WLP wafer level package
4 Technology of device embedded substrate
4.1 Basic structures
Figure 1 shows an example of device embedding structures in the fabrication process of a
device embedded substrate. Active and passive devices are connected to each other by
interlayer vias and/or conductor patterns. Insulating layers are formed using insulating materials

– 8 – IEC TS 62878-2-1:2015 © IEC 2015
with vias for connection of inside conductor patterns to the conductor patterns formed on the
surface(s) of the substrate. Figure 2 shows the substrate with connections using pads. Figure 3
shows the board using via connections.
The insulating layer includes rigid and flexible insulating resins such as phenol resin, epoxy
resin, polyimide resin and modified polyimide resin, which may be reinforced with glass cloth,
aramid cloth or paper. Interconnections include conventional interconnections to terminals of an
embedded device and to a land for SMD, and formation of terminals by copper plating or vias
using conductive paste.
This part of IEC 62878 does not specify a specific fabrication process of a device embedded
substrate, via diameter/land diameter, conductor width/conductor spacing or a conductor line
density.
IEC
IEC
a) Active device b) Passive device
IEC
IEC
c) Discrete and sheet type device d) Assembled device
IEC
e) Passive device
Figure 1 – Examples of device embedded substrate

– 9 – IEC TS 62878-2-1:2015 © IEC 2015

C
A B F D
F
C
A
E
IEC
Key
A Layer connection (via)
B Solder connection
C Pattern formation
D Embedded active device
E Base
F Solder resist
Figure 2 – Completed device embedded substrate (pad connection)

C D
B
A
E
F
IEC
Key
A Embedded with terminals upward
B Copper plated connection
C Copper plated via
D Embedded active device
E Base
F Solder resist
Figure 3 – Completed device embedded substrate (via connection)
4.2 Technology of device embedded substrate
There are two types of device embedded substrates. One type consists of mounting active
and/or passive devices on a base substrate, then covering with organic resin; the other type
consists of forming a device on a substrate and then covering it with organic resin.
Figure 4 shows the structure of a pad connection type substrate in which the active device is
connected by pad onto the passive device embedded ceramics base. The device embedded
substrate also includes composite type substrates which consist of mass produced inorganic

– 10 – IEC TS 62878-2-1:2015 © IEC 2015
ceramics, including LTCC (low temperature co-fired ceramics, hereafter referred to as ceramics)
substrates.
IEC
Key
A Active device
B Base
C Embedding using resin
D Ceramic substrate
E Embedded devices in ceramic
Figure 4 – Structure of a pad connection type substrate
on a passive device embedded ceramics base
In the via structure type, as shown in Figure 5, the ceramic substrate is used as a base on which
active and passive devices are mounted and the entire body is covered with organic resin.
However, details of inorganic ceramic substrates are not specified in this part of IEC 62878.
Such a ceramic substrate is treated just as a base of a device embedded substrate.
IEC
Key
A Active device
B Base
C Resin embedding
D Ceramic substrate
Figure 5 – Structure of a device embedded substrate using
a ceramic board as the base (via connection type)
Classification of device embedding is given in Table 1. Active devices include for example bare
die, wafer level package (WLP), ball grid array (BGA), land grid array (LGA), quad flat no lead
package (QFN), small outline J-leaded package (SOJ) and quad flat package (QFP).
Passive devices include a chip component, a complex chip component like an array and an
integrated passive device (IPD). Module and MEMS may be embedded into the substrate after

– 11 – IEC TS 62878-2-1:2015 © IEC 2015

packaging and molding. The components formed during substrate formation are not covered by
this specification and are not included in Table 2.
There are two types of embedding formed passive components. The first type consists of
forming passive components using thick film or thin film technology on the base of silicon or
compound semiconductor and/or on the stacked chip at the wafer level or on
package-on-package (PoP). The second type consists of using a sheet-type passive device on
an organic substrate followed by the embedding of other devices.
Table 1 – Classification of device embedding
Device
Classification Item Embedding Bonding Schematics
terminals
Die bonding Peripheral Wire bonding

Flip chip Peripheral area Flip chip
Bare die
bonding array bonding
Via connection
Peripheral area
Die bonding
array
(Plating, paste)
Soldering
Peripheral area
Active device Mounting
Conductive
array
paste
Wafer level
package
Via connection
Peripheral area
Die bonding
array
(Plating, paste)
Soldering
Mounting BGA, LGA, QFN
Conductive
paste
Package
Via connection
Mounting BGA, LGA, QFN
(Plating, paste)
Rectangular
chip
Mounting Through hole
Rod type chip
Rectangular Soldering
chip
Chip component Mounting
Conductive
Rod type chip paste
Via connection
Rectangular
Mounting
chip
(Plating, paste)
Soldering
Passive
Rectangular
Mounting
Conductive
device
chip
paste
Module chip
component
Via connection
Rectangular
Mounting
chip
(Plating, paste)
Soldering
Mounting IPD
Conductive
paste
Integrated passive
device
Via connection
Mounting IPD
(Plating, paste)
Soldering
Packaging and
Module Mounting Arbitrary
Conductive
molding
paste
– 12 – IEC TS 62878-2-1:2015 © IEC 2015
Device
Classification Item Embedding Bonding Schematics
terminals
Via connection
Mounting Arbitrary
(Plating, paste)
Soldering
Mounting Arbitrary
Conductive
paste
Packaging and
MEMS
molding
Via connection
Mounting Arbitrary
(Plating, paste)
Table 2 – Formed embedded device into the substrate
Device
Classification Item Embedding Bonding Schematics
terminals
Thin film
Silicon
sputtering
Active device Formed
Thick film Semiconducting
screen printing polymer
Double through
Copper plating
hole
Via connection
(Plating, paste)
Laminate
Etching
material
Passive device Formed
Etching Film
Screen printing Polymer
Ferromagnetic
Transfer
ceramics
Lamination Seeding
Spin coating Polymer
4.3 Structures of device embedded substrates and terms used in this specification
Structures and fabrication processes of device embedded substrates are illustrated in Table 3.
A base substrate is necessary for a device embedded substrate to embed active and passive
devices. Most of the base substrates are multilayer substrates and/or build-up substrates which
are made of insulating resin board; insulating sheet, metal sheet and film carrier can also be
used. Table 3 shows the methods to embed active or passive devices and then connect devices
to the surface conductor by plated through hole vias and/or conductive paste, and checking
items during the fabrication process.
This specification, however, does not cover active devices formed on silicon interposer,
compound semiconductor substrates or a printed wiring board and formed passive device
(resistor, capacitor or inductor). On the other hand it covers an inductor formed together with the
formation of conductor pattern and the capacitor with via-in-via structure.

– 13 – IEC TS 62878-2-1:2015 © IEC 2015

Table 3 – Embedded device structure and fabrication process
Structure
Process Item To check
Pad bonding Via connection
Opening,
1 Base
short-circuiting
2 Mounting Position accuracy
Connection,
-
3 Pad bonding
conduction
Microvoid
4 Embedding Board thickness
Flatness
Hole position
Terminal position
5 Via forming
Resistance to
chemicals
Thicknesses of
copper plating and
-
6 Via connection
conductive paste
Microvoid
Pattern formation
7 Open, short
(multi-layer）
Surface treatment
8 Visual inspection
(Solder mask,
etc.)
5 Jisso mounting and interconnection
5.1 General
There are two types of terminal connection. One type consists of connecting the terminals of an
embedded device to connecting pads formed on the base, and the other consists of forming
connecting vias on the device after embedding. The device is connected to pads on the base
using conventional semiconductor and SMD mounting techniques and then the device is
embedded. In the second type, the device is connected to a conductor pattern after it has been
embedded by copper plating or conductive paste. Both device mounting types can be classified
into die-bonding and mounting methods, as shown in Table 4.

– 14 – IEC TS 62878-2-1:2015 © IEC 2015
Table 4 – Jisso mounting and interconnection of device embedded substrate
Interconnection
Jisso mounting Device Structure
Process Interconnection
Wire bonding
Metal bonding
Die bonding Chip
Metal bonding
Flip-chip bonding
Contact connection Contact
Wafer level Soldering
package
(WLP)
Conductive paste
Package
Pad bonding
Rectangular Soldering
chip
Soldering
Reflow polymer
bonding
Mounting conductive paste
Conductive paste
Rod-type chip
Module Soldering
Conductive paste
MEMS
– 15 – IEC TS 62878-2-1:2015 © IEC 2015

Interconnection
Jisso mounting Device Structure
Process Interconnection
Chip Copper plating
Wafer level
Die bonding
package
(WLP)
Conductive paste
Copper plating
Package
conductive paste
Via connection
Via bonding
Rectangular Copper plating
chip
Mounting
Rod-type chip
Module
Conductive paste
Copper plating
MEMS Via connection
Conductive paste
Shape and surface treatment of terminals of the device to be embedded should be agreed
between user and supplier of the device.
5.2 Interconnections and structures of device embedded substrate
Figure 6 shows each section of a device embedded substrate and its name. See IEC 60194 for
the terms used in this part of IEC 62878. Additions to IEC 60194 for the terms specific to device
embedding technology are being reviewed. The number of layers is counted after device
embedding is complete as L1, L2 to L6 (in case of 6 layers) counting from the top layer.
The structure of the device embedded substrate is illustrated by means of the structure of the
build-up substrate. Figure 7 shows a typical base structure and Figure 8 a cavity structure.
Figure 9 shows the structure for an insulating base and Figure 10 for a base using a conductive
carrier or metal sheet. Use of ceramic substrate in device embedding is stated here for technical
information. Figure 11 and Figure 12 show ceramic board as the wiring board base and ceramic
board used as base, respectively.
A
B
L1
L2
L3
C
L4
L5
L6
IEC
Key
A Active device
B Embedded device connecting pad
C Base
Figure 6 – Entire structure of device embedded substrate

– 16 – IEC TS 62878-2-1:2015 © IEC 2015
A
L2
L3
B
L4
L5
IEC
Key
A Embedded device connecting pad
B Base
Figure 7 – Base (typical structure)
A
L2
L3
B
L4
L5
IEC
Key
A Embedded device connecting pad
B Base
Figure 8 – Base (cavity structure)
A
IEC
Key
A Insulating material (base, prepreg, etc.)
Figure 9 – Base (insulator)
A
IEC
Key
A Copper foil
Figure 10 – Base (Conductive carrier – metal plate)

– 17 – IEC TS 62878-2-1:2015 © IEC 2015

IEC
Key
A Ceramic wiring board
B Base
C Embedded component in ceramic board
Figure 11 – Passive device embedded ceramic board used as a base
A
B
IEC
Key
A Ceramic wiring board
B Base
Figure 12 – Ceramic board used as base (ceramic)
5.3 Device embedding by conventional process
Figure 13 to Figure 18 show various cases of device embedding in conventional mounting
techniques, electric connection after embedding of various types of devices, embedding device
to more than one layer, device embedding with a resin base, and also the use of a conductor
layer and metal sheet/copper foil.
A
D
C
B
E
IEC
Key
A Active device
B Embedded with upward terminal
C Encapsulant
D Bonding wire
E Base
Figure 13 – Wire bonding connection and embedding of active device bare die

– 18 – IEC TS 62878-2-1:2015 © IEC 2015
C
B A
D
IEC
Key
A Active device
B Embedded with downward terminal
C Soldering
D Base
Figure 14 – Soldering connection and embedding of active device
B
A
IEC
Key
A Passive device
B Soldering
Figure 15 – Soldering connection of square type passive device
A
B
IEC
Key
A Active device
B Conductive adhesive
Figure 16 – Conductive resin connection and embedding of active device

– 19 – IEC TS 62878-2-1:2015 © IEC 2015

B A
IEC
Key
A Passive device
B Conductive adhesive
Figure 17 – Conductive resin connection and embedding of square type passive device
B
A
C
IEC
Key
A Passive device
B Soldering
C Two through holes
Figure 18 – Soldering connection into through hole and embedding of passive device
5.4 Device embedding using vias
Figure 19 to Figure 27 show various cases of device embedding using vias.
D
C
B
A
E
IEC
Key
A Active device
B Embedded with upward terminals
C Copper plating connection
D Copper plated via
E Base
Figure 19 – Connection by copper plating after embedding of active device

– 20 – IEC TS 62878-2-1:2015 © IEC 2015
B
A
IEC
Key
A Passive device
B Copper plating connection
Figure 20 – Connection by copper plating after embedding
of square type passive device
B
A
IEC
Key
A Active device
B Conductive paste connection
Figure 21 – Conductive paste connection after embedding
of active device package
B
A
IEC
Key
A Passive device
B Conductive paste connection
Figure 22 – Conductive paste connection after embedding
of square type passive device chip

– 21 – IEC TS 62878-2-1:2015 © IEC 2015

A
C
B
IEC
Key
A Active device
B Passive device
C Base
Figure 23 – Device embedded substrate for device embedding in multi-layers
C
A
B
IEC
Key
A Active device
B Base
C Conductive layer in embedding layer
Figure 24 – Embedding of devices over multiple layers
A
C
B
IEC
Key
A Active device
B Passive device
C Base (insulator)
Figure 25 – Resin base substrate

– 22 – IEC TS 62878-2-1:2015 © IEC 2015
IEC
Key
A Active device
B Soldering
C Base (Copper foil)
Figure 26 – Conductor and metal sheet/copper foil as base substrate
B
A
C
D
IEC
Key
A Active device
B Molding compound
C Ceramic substrate
D Base
Figure 27 – Device embedded substrate using passive device embedded
ceramic substrates as base substrate – Second type
6 Naming of each section
6.1 General
The structure of a device embedded board is described in 5.2. Positions and names of the parts
of a board are specified here to technically understand the construction and structure of a device
embedded board and to establish a common understanding in design and/or production of
boards.
6.2 General definition of top and bottom surfaces
The top surface of a device embedded board is defined as the side where more electrical
terminals (pads) exist. The bottom surface is defined as the side to which a board is connected
to a printed wiring board (hereafter called mother board) and this is shown as Figure 29.
Although the bottom surface may have more I/O terminals (pads) than the top surface, this side
is still defined as the bottom surface. Figure 28 shows structure of a completed device
embedded board and Figure 29 shows cross section of the completed device embedded board
mounted on a mother board. User and supplier may define the top and bottom surfaces
otherwise even when different from the definition given here.

– 23 – IEC TS 62878-2-1:2015 © IEC 2015

B
D
A
C
B
E
IEC
Key
A Embedded component D Top surface
B Surface mounted device E Bottom surface
C Base
Figure 28 – Definition of top and bottom surfaces
B
D
A
C
F
E
G
IEC
Key
A Embedded component E Bottom surface
B Surface mounted device F Connecting terminal (BGA or LGA)
C Base G Printed wiring board (mother board)
D Top surface
Figure 29 – Definition of top and bottom surfaces (mounting of a mother board)

– 24 – IEC TS 62878-2-1:2015 © IEC 2015
6.3 Naming of layers and interconnection position
Names and symbols of layers in a device embedded board are illustrated in Figure 30. Each
layer is numbered as L1, L2 to L6 (in case of 6 layers) from the top surface. The number
indicates the order of the layer with respect to the top surface.
C
A
L1
L2
L3
B
L4
L5
L6
D
IEC
Key
A Embedded component C Top surface
B Base D Bottom surface
Figure 30 – Names of layers in pad connection
In the case of via connection, the position of connecting terminals of the embedded device is
different from the surrounding layer number. The component symbol and connecting position(s)
are defined as illustrated in Figure 31 in order to clarify the interconnecting positions of the
embedded device and of its electrical terminals with respect to construction design, pattern
design, board fabrication and jisso (assembly).
It is recommended to use the component symbols and names as shown in a circuit diagram to
use 2 to 4 indications. The position of interconnection in the case of die-bonding or mounting of
a device embedded device may be expressed using another name in addition to the name of the
layer in which the device is embedded.
The surface of a device is upward facing. Use upward (U) when connecting terminals are in the
upward facing surface, and downward (D) when the terminals are in the downward facing
surface.
A three digit number is used if multiple components are embedded and/or multiple connection
terminals are in the same layer. The left side number indicates the interconnecting layer number
and the right side number indicates the layer position of the embedded component. If there are
multiple layers involved, numbers 1, 2 indicate the layers from the top for upward and numbers
1, 2 indicate the layers from the bottom for downward. The second number may be omitted if
there is only one embedded component in a layer. See the example in Figure 31.
Figure 31 shows additional information on the interconnection position. The active device is
mounted on the L2 layer and connected to the first layer with upward direction. In this case, the
name of the interconnection layer is expressed as L2-U11. The last digit 1 indicates the number
of the embedded component. Passive components mounted on the L5 layer are connected to
L6 with downward direction. In this case, the name of the interconnection layer is expressed as
L5-D61.
A virtual layer is used as a virtual conductor layer and as the connecting points. The terminal
connection design of an embedded device is carried out by first establishing the connection and
hole machining data A and B, then the connection and hole machining data C and D for L2 and
L5 (in the case of the above structure). The terminal setting may be omitted if a via connection
and the positions of embedded device terminals and the conduction layer are the same.

– 25 – IEC TS 62878-2-1:2015 © IEC 2015

H
J
B
A
E
L1
F＝L2-U11
L2
L3
D
L4
L5
G＝L5-D61
L6
C
B
K
I
IEC
Key
A Embedded active device G Name of the layer between L5 and L6
B Connecting terminal H Connection and machining data from L1 to a virtual layer
(L2-U11)
C Embedded passive device I Connection and machining data from L1 to L2
D Base J Connection and machining data from L6 to virtual layer
(L5-D61)
E Terminal position K Connection and machining data from L6 to L5
F Name of the layer between L1 and L2
Figure 31 – Additional information concerning the interconnection position
Figure 32 shows the interconnection position. Active device (xxxx) is mounted on the L2 layer
and connected t
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