Semiconductor devices - Bias-temperature stability test for metal-oxide, semiconductor, field-effect transistors (MOSFET) - Part 1: Fast BTI test for MOSFET

IEC 62373-1:2020 provides the measurement procedure for a fast BTI (bias temperature instability) test of silicon based metal-oxide semiconductor field-effect transistors (MOSFETs).
This document also defines the terms pertaining to the conventional BTI test method.

Dispositifs à semiconducteurs - Essai de stabilité de température en polarisation pour transistors à effet de champ métal-oxyde-semiconducteur (MOSFET) - Partie 1: Essai rapide de BTI pour les MOSFET

L’IEC 62373-1:2020 fournit la méthode de mesure pour un essai rapide de BTI (instabilité en température sous polarisation) des transistors à effet de champ métal-oxyde-semiconducteurs (MOSFET) à base de silicium.
Le présent document définit également les termes relatifs à la méthode d’essai de BTI conventionnelle.

General Information

Status
Published
Publication Date
14-Jul-2020
Technical Committee
Current Stage
PPUB - Publication issued
Completion Date
15-Jul-2020
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IEC 62373-1:2020 - Semiconductor devices - Bias-temperature stability test for metal-oxide, semiconductor, field-effect transistors (MOSFET) - Part 1: Fast BTI test for MOSFET
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IEC 62373-1
Edition 1.0 2020-07
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Semiconductor devices – Bias-temperature stability test for metal-oxide,
semiconductor, field-effect transistors (MOSFET) –
Part 1: Fast BTI test for MOSFET
Dispositifs à semiconducteurs – Essai de stabilité de température en
polarisation pour transistors à effet de champ metal-oxyde-semiconducteur
(MOSFET) –
Partie 1: Essai rapide de BTI pour les MOSFET
IEC 62373-1:2020-07(en-fr)
---------------------- Page: 1 ----------------------
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---------------------- Page: 2 ----------------------
IEC 62373-1
Edition 1.0 2020-07
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Semiconductor devices – Bias-temperature stability test for metal-oxide,
semiconductor, field-effect transistors (MOSFET) –
Part 1: Fast BTI test for MOSFET
Dispositifs à semiconducteurs – Essai de stabilité de température en
polarisation pour transistors à effet de champ metal-oxyde-semiconducteur
(MOSFET) –
Partie 1: Essai rapide de BTI pour les MOSFET
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.080.30 ISBN 978-2-8322-8610-4

Warning! Make sure that you obtained this publication from an authorized distributor.

Attention! Veuillez vous assurer que vous avez obtenu cette publication via un distributeur agréé.

® Registered trademark of the International Electrotechnical Commission
Marque déposée de la Commission Electrotechnique Internationale
---------------------- Page: 3 ----------------------
– 2 – IEC 62373-1:2020 © IEC 2020
CONTENTS

FOREWORD ........................................................................................................................... 4

INTRODUCTION ..................................................................................................................... 6

1 Scope .............................................................................................................................. 7

2 Normative reference ........................................................................................................ 7

3 Terms and definitions ...................................................................................................... 7

4 Test equipment ................................................................................................................ 9

4.1 Equipment .............................................................................................................. 9

4.1.1 Wafer prober ................................................................................................... 9

4.1.2 Measurement equipment ................................................................................. 9

4.2 Recommendation for handling ............................................................................... 10

5 Test sample ................................................................................................................... 10

5.1 Sample ................................................................................................................. 10

5.1.1 General ......................................................................................................... 10

5.1.2 Channel length (gate length) .......................................................................... 10

5.1.3 Channel width (gate width) ............................................................................ 10

5.1.4 Structure ....................................................................................................... 10

5.1.5 Wafer process ............................................................................................... 11

5.2 Antenna protection diode ...................................................................................... 11

5.3 Number of samples ............................................................................................... 11

6 Procedure ...................................................................................................................... 12

6.1 General remarks on measurement time ................................................................. 12

6.2 Definition of measurement parameter.................................................................... 12

6.2.1 Expression of degradation parameters ........................................................... 12

6.2.2 Measurement in weakly inverted region ......................................................... 13

6.2.3 Measurement in subthreshold region ............................................................. 13

6.2.4 Measurement of I degradation (I , I ) ................................................ 14

D Dsat Dlin

6.3 Test ...................................................................................................................... 14

6.3.1 Test flow ........................................................................................................ 14

6.3.2 Fast voltage switching ................................................................................... 15

6.3.3 Temperature .................................................................................................. 16

6.3.4 Electric field strength E .............................................................................. 16

6.3.5 Read point ..................................................................................................... 16

6.3.6 Final test time ................................................................................................ 16

6.4 Lifetime estimation ................................................................................................ 17

6.4.1 Procedure for estimating the degradation at end of life .................................. 17

6.4.2 Procedure for estimating the lifetime on the targeted criteria ......................... 18

Annex A (informative) Recovery effect of BTI ....................................................................... 19

Annex B (informative) Selection of a wide device [2] ............................................................ 20

Bibliography .......................................................................................................................... 22

Figure 1 – Degradation (∆V ) recovering by BTI conditions removing with time ...................... 6

Figure 2 – I – V curve to explain V .......................................................................... 8

D GS th-ext

Figure 3 – Connection between MOSFET electrodes and external terminals ......................... 10

Figure 4 – Example of antenna protection circuit for BULK process ...................................... 11

Figure 5 – Measurement time dependence of recovery effect ................................................ 12

---------------------- Page: 4 ----------------------
IEC 62373-1:2020 © IEC 2020 – 3 –

Figure 6 – Calculation method of V degradation ................................................................. 14

Figure 7 – Comparison of BTI flowchart ................................................................................ 15

Figure 8 – Switching schematic of fast BTI ............................................................................ 16

Figure A.1 – Recovery time dependence of Pch BTI ............................................................. 19

Figure B.1 – Typical BTI induced variance dependence on W ............................................... 21

Figure B.2 – Possible MOSFET layout to be adopted with narrow device .............................. 21

---------------------- Page: 5 ----------------------
– 4 – IEC 62373-1:2020 © IEC 2020
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
BIAS-TEMPERATURE STABILITY TEST FOR METAL-OXIDE,
SEMICONDUCTOR, FIELD-EFFECT TRANSISTORS (MOSFET) –
Part 1: Fast BTI test for MOSFET
FOREWORD

1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising

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International Standard IEC 62373-1 has been prepared by IEC technical committee 47:

Semiconductor devices.
The text of this International Standard is based on the following documents:
FDIS Report on voting
47/2627/FDIS 47/2637/RVD

Full information on the voting for the approval of this International Standard can be found in

the report on voting indicated in the above table.

This document has been drafted in accordance with the ISO/IEC Directives, Part 2.

---------------------- Page: 6 ----------------------
IEC 62373-1:2020 © IEC 2020 – 5 –

A list of all parts in the IEC 62373 series, published under the general title Semiconductor

devices – Bias-temperature stability test for metal-oxide, semiconductor, field-effect

transistors (MOSFET), can be found on the IEC website.

The committee has decided that the contents of this document will remain unchanged until the

stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to

the specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.

IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates

that it contains colours which are considered to be useful for the correct

understanding of its contents. Users should therefore print this document using a

colour printer.
---------------------- Page: 7 ----------------------
– 6 – IEC 62373-1:2020 © IEC 2020
INTRODUCTION

BTI (bias temperature instability) degradation of semiconductor devices is a crucial failure.

IEC 62373:2006 provides a method to test for this failure.

With advances in technology, the magnitude of recovery for BTI degradation has been

remarkable. Recovery from BTI degradation occurs in microseconds to milliseconds after

removing or reducing gate stress. Figure 1 below shows experiment data of V shift which is

stressed in BTI condition for 1 000 s and not stressed after that [1] . It shows that the

degradation is rapidly recovered, to about 40 % in a few seconds right after removing the

stress at 1 000 s. Therefore, a fast measurement method is necessary to avoid this effect and

to determine this degradation with exactitude.
Key
∆r ratio of V degradation amount to maximum degradation;
t stress or recovery time, expressed in seconds.
Figure 1 – Degradation (∆V ) recovering by BTI conditions removing with time

However, the existing test, described in IEC 62373, suffers from the disadvantage that the

recovery process starts as soon as the stress is reduced while making the fairly lengthy set of

measurements that establish the shift in threshold voltage. The procedure described in this

standard uses an alternative method for measuring degradation that, by taking very little time,

minimizes the partial recovery that occurs during the measurement.
_____________
Numbers in square brackets refer to the Bibliography.
---------------------- Page: 8 ----------------------
IEC 62373-1:2020 © IEC 2020 – 7 –
SEMICONDUCTOR DEVICES –
BIAS-TEMPERATURE STABILITY TEST FOR METAL-OXIDE,
SEMICONDUCTOR, FIELD-EFFECT TRANSISTORS (MOSFET) –
Part 1: Fast BTI test for MOSFET
1 Scope

This part of IEC 62373 provides the measurement procedure for a fast BTI (bias temperature

instability) test of silicon based metal-oxide semiconductor field-effect transistors (MOSFETs).

This document also defines the terms pertaining to the conventional BTI test method.

2 Normative reference
There are no normative references in this document.
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.

ISO and IEC maintain terminological databases for use in standardization at the following

addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
3.1
nominal power supply voltage

suitable value of the voltage used to designate the power supply of the technology

3.2
drain – source voltage
voltage between the drain and the source
3.3
gate – source voltage
voltage between the gate and the source
3.4
well – source voltage
voltage between the well and the source
3.5
drain current
current monitored for drain terminal when V is zero
---------------------- Page: 9 ----------------------
– 8 – IEC 62373-1:2020 © IEC 2020
3.6
constant current threshold voltage
th-ci
V at which drain current is equal to selected I
GS D
Note 1 to entry: This definition is expressed by the following equation.
(1)
V V when I I ×
th−ci GS D D0
where
V is constant current threshold voltage where;
th-ci
I is drain current (arbitrary);

I is constant value, which is recommended at V < V (typically selected from 50 nA to 300 nA);

D0 GS th-ext
W is channel width;
L is channel length.

Note 2 to entry: If V is over V , it is possible that the mobility degradation affects V and if V is V ,

GS th-ext th-ci GS th-ext
the impact of the density of interface states to V shift may not be detected.
3.7
extrapolated threshold voltage
th-ext

gate source voltage at which the extrapolated maximum slope of the curve of drain current

versus gate source voltage intercepts the drain-current axis
SEE: Figure 2.
Key
A I – V curve;
D GS
C extrapolated maximum slope of the I – V curve;
D GS
V extrapolated threshold voltage.
th-ext
Figure 2 – I – V curve to explain V
D GS th-ext
3.8
saturated drain current
Dsat

drain current when the transistor is biased in the saturation region and the measure condition

is V = V = V
DS GS DD
= =
---------------------- Page: 10 ----------------------
IEC 62373-1:2020 © IEC 2020 – 9 –
3.9
linear drain current
Dlin
drain current at linear region (V = 0,05 V to 0,1 V) and V = V
DS GS DD
3.10
gate source voltage for measurement
GS-meas
V which is applied in measurement duration
3.11
drain current for measurement
D-meas
drain current at V = V
GS GS-meas
3.12
dielectric electric field strength
electric field strength in the gate dielectric
Note 1 to entry: The general formula for E is
(2)
E =
where
E is electric field strength of gate dielectric;
V is gate dielectric applied voltage;
t is gate dielectric thickness.

t is a parameter used for inline monitoring determined by CV analysis at inversion condition. It is important to

point out that the applied voltage is not necessarily the voltage across the dielectric. Ultrathin dielectrics exhibit

quantum confinement effects and gate electrode depletion effects effectively reducing the voltage across the

dielectric. The method of determining t or a reference to the documented standard should be included in the data

report.
4 Test equipment
4.1 Equipment
4.1.1 Wafer prober

A wafer prober equipped with a hot chuck is used. The temperature should be kept constant

(within ±1 °C is recommended) during stress and measurement. All time intervals should be

recorded to an accuracy of 1 %. These include the period from the first application of stress to

the start of each measurement, and the duration of each measurement before the stress is re-

applied.

Since some equipment is designed with a tolerance of ±3 °C, it is necessary to confirm that it

is within ±1 °C by actual measurement on the chuck.
4.1.2 Measurement equipment

Measurement instruments with fast voltage switching are used for the DC characteristics of

MOSFETs. The fast switching shall be in a few ms (it is recommended in a few µs, if possible).

The accuracy should be maintained at high temperature.
---------------------- Page: 11 ----------------------
– 10 – IEC 62373-1:2020 © IEC 2020
4.2 Recommendation for handling

When it is available, it is recommended to use ESD protective equipment (wrist strap etc.) to

prevent damage to the test sample.
5 Test sample
5.1 Sample
5.1.1 General
One MOSFET, as described in 5.1.2 to 5.1.5, is used.
5.1.2 Channel length (gate length)

It is recommended to use the designed minimum channel length of the targeted technology or

production when individual specifications are not specifically defined, or when the minimum

channel length does not yield a worse BTI. If necessary, channel length dependence may be

confirmed by evaluating another channel length.

NOTE In some technologies the worst BTI is associated with the longest channel length.

5.1.3 Channel width (gate width)

The measured variability of BTI shifts is strongly dependent on the selected channel width. It

is recommended to define the channel width at which the measurement is steady (see

Annex B). It is better for it to be determined through pre-test. If there is no special

requirement, a channel width from 1 μm to 20 μm is recommended.
5.1.4 Structure

It is recommended that four electrodes (gate, source, drain, substrate) are connected to

individual external terminals Figure 3a). A common gate/source terminal structure

(see Figure 3b]) shall not be used.
a) Individual terminal b) Common gate/source terminal
Key
G gate terminal;
S source terminal;
D drain terminal;
B substrate terminal.
Figure 3 – Connection between MOSFET electrodes and external terminals

The well terminal used during stress/measurement shall be at the same bias conditions as in

operation (typically V = 0 if bulk). To minimize parasitic voltage drops between the probe

pads and the device terminals (V ), the wiring resistances (R ) from the probe pads to

device W

the device gate, source, drain, and well are selected such that the voltage drop (I × R ) is

less than 1 % V .
device
---------------------- Page: 12 ----------------------
IEC 62373-1:2020 © IEC 2020 – 11 –
5.1.5 Wafer process
It is strongly recommended that the steps of the wafer process, such as impurity

concentration, thermal treatment, wiring process, be identical to those required by the

targeted technology. The impact of process damage can be mitigated when the multi-layered

metallization process is simplified for sample preparation. It is necessary to carefully consider

the result.
5.2 Antenna protection diode

According to the design manual, an antenna protection diode shall be added to the gate

electrode (see Figure 4) to avoid antenna damage. However, if it is necessary to consider RC

delay for fast BTI measurement, unnecessary or excessive antenna protection diode should

not be implemented. Drain current should be measured to an accuracy better than 0,2 %.

Owing to the transient effect of switching the drain voltage, the time-constant at the input of

the instrument used to measure very low levels of drain current should be taken into

consideration when the measurement duration is very short. Sensitivity to possible stray

voltages should also be considered.
Key
Components Terminals
K1 MOSFET G gate terminal
K2 protection diode S source terminal
D drain terminal
B substrate terminal
Figure 4 – Example of antenna protection circuit for BULK process
5.3 Number of samples

Depending on the measured variability of the BTI shifts for a given device, an adequate

sample size is required to achieve an assumed statistical confidence level, see Annex B. A

minimum of four samples is recommended for each test condition for a large channel width

(recommended in 5.1.3).
---------------------- Page: 13 ----------------------
– 12 – IEC 62373-1:2020 © IEC 2020
6 Procedure
6.1 General remarks on measurement time

The amount of degradation depends on the measurement time because the recovery effect of

a Pch BTI is considerable. Making a set of measurements of drain current vs. gate source

voltage (I – V ), to determine the threshold voltage directly, takes a comparatively long

D GS

time and the recovery effect can be comparatively large, see Annex A. The measurement time

shall be shorter than a few ms. And if possible, the measurement time should be under 10 µs.

The fast measurement method by using common DC measurement system is the single-point

measurement of drain current I and the measurement time should be made shorter. It is

defined as “fast BTI” method. The fast BTI method compared to the conventional BTI method

is described in Figure 5. The conventional BTI test flow, which is based on IEC 62373, is

exhibited simply in comparison with the fast BTI method (see Figure 5).
Key
t time;
V ground level;
V measurement voltage;
V stress voltage;
a period of I – V measurement;
D GS
b period of single point I measurement;

Dotted line applied V and V degradation profile in conventional BTI measurement method;

GS th
Solid line applied V and V degradation profile in fast BTI measurement method.
GS th
Figure 5 – Measurement time dependence of recovery effect
6.2 Definition of measurement parameter
6.2.1 Expression of degradation parameters

The degradation parameter is the change of threshold voltage at the selected drain current.

However, the measurement of a single I point cannot express the degradation of V ,

D th
therefore I values are converted into V by using initial I – V parameters. I
D-meas th D GS D-meas

and the initial I -V parameters shall be measured at the same temperature as a stress

D GS
condition.
---------------------- Page: 14 ----------------------
IEC 62373-1:2020 © IEC 2020 – 13 –
6.2.2 Measurement in weakly inverted region
In this procedure, it is recommended that V be specified below V to minimize the
GS-meas th-ext

effect of mobility degradation. In this case, the degradation can be converted from I into V

D th
by the subtraction between V and V at the point of measured I in the initial I –
...

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