ISO/IEC 14575:2000

Information technology - Microprocessor systems - Heterogeneous InterConnect (HIC) (Low-Cost, Low-Latency Scalable Serial Interconnect for Parallel System Construction)

The construction of high-performance systems with parallel communications, parallel processing, and/or parallel I/O demands a fast, low-cost, low-latency interconnect. It must be fast and low-latency, otherwise it will be the limiting factor in system performance; and it must be low-cost, or it will dominate the system cost. This standard has been developed to complement recent technical developments of highly integrated, low-power interconnect technology implemented in high-volume commodity VLSI processes, and to exploit the simplifications in encodings and protocols resulting from the use of relatively reliable media over relatively short distances.

General Information

• Status: Published
• Publication Date: 10-Jul-2000
• ICS: 01 - GENERALITIES. TERMINOLOGY. STANDARDIZATION. DOCUMENTATION
• ICS: 35.160 - Microprocessor systems
• Technical Committee: ISO/IEC JTC 1/SC 25 - Interconnection of information technology equipment
• Current Stage: PPUB - Publication issued
• Start Date: 30-Nov-1998
• Completion Date: 11-Jul-2000

Standards Content (Sample)

INTERNATIONAL ISO/IEC
STANDARD
14575
IEEE
Std 1355
First edition
2000-07
Information Technology –
Microprocessor Systems – Heterogeneous
InterConnect (HIC) (Low-Cost, Low-Latency
Scalable Serial Interconnect for
Parallel System Construction)
Reference number
ISO/IEC 14575:2000(E)
IEEE Std 1355, 1998 Edition

---------------------- Page: 1 ----------------------
Abstract: Enabling the construction of high-performance, scalable, modular, parallel systems
with low system integration cost is discussed. Complementary use of physical connectors and
cables, electrical properties, and logical protocols for point-to-point serial scalable
interconnect, operating at speeds of 10 200 Mb/s and at 1 Gb/s in copper and optic
technologies, is described.
Keywords: flow control, encoding schemes, OMI/HIC, packet routing, parallelism, point-to-
point serial scalable interconnect, protocols, routing fabric, serial links, serialization, silicon
integration, switch chip, transaction layer, wormhole routing.

––––––––––––
The Institute of Electrical and Electronics Engineers, Inc.
345 East 47th Street, New York, NY 10017-2394, USA
Copyright © 1998 by the Institute of Electrical and Electronics Engineers, Inc.
All rights reserved. First published in 1998.
ISBN 2-8318-5321-4
No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without
the prior written permission of the publisher.

---------------------- Page: 2 ----------------------
INTERNATIONAL ISO/IEC
STANDARD
14575
IEEE
Std 1355
First edition
2000-07
Information Technology –
Microprocessor Systems – Heterogeneous
InterConnect (HIC) (Low-Cost, Low-Latency
Scalable Serial Interconnect for
Parallel System Construction)
Sponsor
Bus Architecture Standards Committee
of the IEEE Computer Society
PRICE CODE
XB
For price, see current catalogue

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– 2 – ISO/IEC 14575:2000(E)
IEEE Std 1355, 1998 Edition
CONTENTS
Page
FOREWORD . 8
INTRODUCTION .9
Clause
1 Scope and object . 15
2 Normative references . 15
3 Definitions. 17
3.1 General. 17
3.2 Glossary . 17
4 Physical media and logical layers . 23
4.1 Physical media. 23
4.2 Logical layers. 24
4.3 Interaction of layers. 27
4.4 Implementations defined in this International Standard . 29
5 DS-SE and DS-DE . 31
5.1 General. 31
5.2 DS-SE: physical medium . 32
5.3 DS-SE signal level . 32
5.4 DS-DE: physical medium. 38
5.5 DS-DE signal level . 44
5.6 DS-SE and DS-DE character level. 46
5.7 DS-SE and DS-DE exchange level . 48
6 TS-FO-02 fiber optic link . 51
6.1 Physical medium . 51
6.2 Signal level . 53
6.3 TS-FO character level . 55
6.4 TS-FO exchange level.
...