ISO/IEC 15776:2001

VME64bus - Specification

The VMEbus specification defines an interfacing system used to interconnect microprocessors, data storage and peripheral control devices in a closely-coupled hardware configuration. Its objectives include allowing communication between devices on the VMEbus without disturbing the internal activities of other devices on the VMEbus, allowing a broad range of design latitude so that the designer can optimize cost and/or performance without affecting system compatibility, and providing a system where performance is primarily device-limited rather than system-interface-limited.  Note that this publication is available not in paper form but as a CD-ROM.

General Information

• Status: Published
• Publication Date: 20-Dec-2001
• ICS: 01 - GENERALITIES. TERMINOLOGY. STANDARDIZATION. DOCUMENTATION
• ICS: 35.160 - Microprocessor systems
• Technical Committee: ISO/IEC JTC 1/SC 25 - Interconnection of information technology equipment
• Current Stage: PPUB - Publication issued
• Start Date: 31-Jan-2001
• Completion Date: 21-Dec-2001

Standards Content (Sample)

INTERNATIONAL ISO/IEC
STANDARD
15776
First edition
2001-12
VME64bus – Specification
Reference number
ISO/IEC 15776:2001(E)

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INTERNATIONAL ISO/IEC


STANDARD 15776



First edition
2001-12



VME64bus – Specification





© ISO/IEC 2001
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– 2 – 15776 © ISO/IEC:2001(E)
CONTENTS
FOREWORD .8
INTRODUCTION.9
1 General.13
1.1 Scope and object .13
1.2 Normative references.13
1.3 VMEbus interface system elements.14
1.4 VMEbus specification diagrams.20
1.5 Specification terminology .22
1.6 Protocol specification .24
1.7 System examples and explanations.25
2 Data transfer bus.25
2.1 Introduction.25
2.2 Data-transfer-bus lines.27
2.3 DTB modules – Basic description .38
2.4 Typical operation.64
2.5 Data-transfer-bus acquisition .73
2.6 DTB timing rules and observations .75
3 Data transfer bus arbitration.120
3.1 Bus arbitration philosophy.120
3.2 Arbitration bus lines.122
3.3 Functional modules .124
3.4 Typical operation.132
3.5 Race conditions between master requests and arbiter grants.141
4 Priority interrupt bus.141
4.1 Introduction.141
4.2 Priority interrupt bus lines.144
4.3 Priority interrupt bus modules – Basic description .146
4.4 Typical operation.159
4.5 Race conditions.165
4.6 Priority interrupt bus timing rules and observations .166
5 Utility bus .
...