ISO/IEC 10859:1997

Information technology- 8-bit backplane interface: STEbus and mechanical core specifications for microcomputers-First edition 1997-06

General Information

• Status: Published
• Publication Date: 23-Jun-1997
• ICS: 01 - GENERALITIES. TERMINOLOGY. STANDARDIZATION. DOCUMENTATION
• ICS: 35.160 - Microprocessor systems
• Technical Committee: ISO/IEC JTC 1/SC 25 - Interconnection of information technology equipment
• Current Stage: PPUB - Publication issued
• Completion Date: 24-Jun-1997

Standards Content (Sample)

INTERNATIONAL
ISO/IEC
STANDARD
First edition
1997-06
Information technology –
8-bit backplane interface: STEbus and mechanical
core specifications for microcomputers
Technologies de l'information –
Interface de fond de panier 8 bits – Bus STE

Reference number
ISO/IEC 10859: 1997(E)
INTERNATIONAL
ISO/IEC
STANDARD
First edition
1997-06
Information technology –
8-bit backplane interface: STEbus and mechanical
core specifications for microcomputers
Technologies de l'information –
Interface de fond de panier 8 bits – Bus STE

 ISO/IEC 1997
All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form or by any
means, electronic or mechanical, including photocopying and microfilm, without permission in writing from the publisher.

ISO/IEC Copyright Office • Case postale 56 • CH-1211 Genève 20 • Switzerland

– 2 – 10859 © ISO/IEC:1997
CONTENTS
Page
FOREWORD . 3

IEEE STANDARD FOR A 8-BIT BACKPLANE INTERFACE: STEBUS

INTRODUCTION . 4

Clause
1 General . 5
2 Functional description. 9
3 Signal lines. 10
4 Arbitration. 16
5 Data transfer protocol . 18
6 Inter-board signalling . 32
7 Electrical specifications . 36
Appendices
A Applicable IEC specifications . 42
B Recommended bus termination arrangement . 43
MECHANICAL CORE SPECIFICATIONS FOR MICROCOMPUTERS
Page
INTRODUCTION . 45
Clause
1 Scope. 46
2 Object . 46
3 References. 46
4 General arrangement. 47
5 Euroboard matrix . 49
6 Euroboard sizes. 50
7 Position of plug-in unit mounted connectors (Board types and box type) . 55

8 Plug-in unit description . 58
9 Plug-in unit dimensions. 58
10 Backplane design and mounting positions . 59
11 Subracks . 83
12 Environmental specifications. 93

10859 © ISO/IEC:1997 – 3 –
Information technology –
8-bit backplane interface:
STEbus and mechanical core specifications

for microprocessors
FOREWORD
ISO (the International Organization for Standardization) and IEC (the International

Electrotechnical Commission) form the specialized system for worldwide standardization.
National bodies that are members of ISO or IEC participate in the development of International
Standards through technical committee established by the respective organization to deal with
particular fields of technical activity. ISO and IEC technical committees collaborate in fields of
mutual interest. Other international organizations, governmental and non-governmental, in
liaison with ISO and IEC, also take part in the work.
In the field of information technology, ISO and IEC have established a joint technical
committee, ISO/IEC JTC1. Draft International Standards adopted by the joint technical
committee are circulated to national bodies for voting. Publication as an International Standard
requires approval by at least 75 % of the national bodies casting a vote.
International Standard ISO/IEC 10859 was prepared by joint technical committee
ISO/IEC JTC1, Information technology, SC 26: Microprocessor system.
This standard is a merging of IEEE Std 1000-1987 and IEEE 1101-1987. It has been submitted
to the National Committees for vote under the Fast Track Procedure.
The numbering of the original clauses remains unchanged.

– 4 – 10859 © ISO/IEC:1997
INTRODUCTION TO IEEE STANDARD
FOR AN 8-BIT BACKPLANE INTERFACE: STEBUS

The initial concept for STEbus was to produce a European version of the STDBus using the

Eurocard form factor with the DIN41612 connector. From that concept STE became known as

STD-European.
When IEEE formed Working Group P1000 the brief specified a Standard 8-Bit Backplane

Interface. At the inaugural meeting of Working Group P1000 it quickly became apparent that

the opportunity was there to create a completely new, modern, high-performance 8-Bit bus, and
all ideas of merely repinning the old STDbus were rapidly forgotten.

At the initial meeting of P1000 it was decided that the bus should be a part of the same family
as VMEbus and Futurebus and as such should be an asynchronous bus with multimaster
capability. Today it is often referred to as the baby brother of VMEbus. Unlike VMEbus though
it was to be processor and manufacturer independent. This has proven to be an excellent
decision as today there are many varied types of processor available on STEbus, from
microcontrollers such as 8031, through Intel's 8085, 8088, and 80188; National
Semiconductor's 32008 and 32016; Motorola's 6809, 68000, and 68008; Zilog's Z80 and Z280;
Hitachi's 64180, and the Inmos Transputer with the promise of more to come.
A presentation was made to a packed audience at the IEE in London, England in early 1983. It
met with critical acclaim. The first article about STEbus was also published about this time in
an international magazine (EDN May 26, 1983).
Work continued internationally and in late 1984 Draft D3.1 was produced. This draft eradicated
the daisy-chain bus request mechanism of D2.0 in favour of a simple solution that allowed
position independence of cards in the rack.
This was the first firm specification and encouraged more manufacturers to look at the bus
seriously. Among them were BICC-Vero, a major manufacturer of Eurocard enclosures and
backplanes, and British Telecom, the UK's Telephone Utility. Market ground zero was early
1985 and since this time the number of manufacturers has continued to grow from
18 companies in Spring 1986 to more than 30 in mid-1987, with over 700 products available.
Much credit and praise is due Tim Elsmore who first conceived the idea for STEbus during his
employment with GMT Electronic Systems Ltd. Paul Borrill was instrumental in negotiating with
IEEE the formation of Working Group P1000 and Bill Shields was appointed Chairman.
This standard was prepared by Working Group P1000 of the Microprocessor Standards
Committee.
10859 © ISO/IEC:1997 – 5 –
Information technology –
8-bit backplane interface:
STEbus and mechanical core specifications

for microprocessors
1 General
1.1 Scope
The overall level of performance that may be achieved by any computer system is determined,
in large part, by the system bus that is used to effect communication between the various
system elements. System performance characteristics, measured in terms of speed, reliability,
suitability to a variety of purposes, and adaptability to changing technology are ultimately
dependent on the particular bus structure that is used and its associated protocols.
This standard defines the IEEE Std 1000 Bus, which may be used to implement general
purpose, high-performance 8-bit microcomputer systems. Such a system may be used in a
stand-alone configuration, or in larger multiple-bus architectures, as a private (or secondary)
bus or a high-speed I/O channel. This standard is applicable to those systems and system
elements with the common commercial designation STEbus. It is intended for those users who
plan to evaluate, implement, or design various system elements that are compatible with the
IEEE 1000 Std Bus system structure.
The physical attributes and method of interconnect utilized by boards and modules conforming
to this standard are derived from several International Electrotechnical Commission (IEC)
standards. These standards, when implemented jointly in a systems environment, result in a
mechanical configuration commonly referred to as Eurocard. Appendix B lists such applicable
standards which, where referenced, are considered as if incorporated with this standard. In
particular, the connector used by IEEE Std 1000 Bus boards is a 64-pin male connector
utilizing the outside two rows (designated a and c rows), specified in IEC 60603-2, and the
mating female connector is used on IEEE Std 1000 Bus backplanes. The recommended size
for IEEE Std 1000 Bus boards is 100 mm × 160 mm (3,937 in × 6,299 in), commonly referred to
as a single height standard depth Eurocard.
The IEEE Std 1000 Bus structure is based on the master-slave concept in which a master,
having gained control of the bus, may address and command slaves. Masters and slaves
communicate with each other by use of an asynchronous interlocked handshake protocol. This
technique allows for the construction of computer systems that incorporate devices of widely
varying speeds. Multiple masters may be implemented within a single system.

Two independent address spaces are supported: memory and I/O. Memory transactions
reference a 1 megabyte physical address space, while I/O transactions reference a 4 kilobyte
physical address space. System integrity during all such transactions is enhanced by provision
of a transfer error signal.
Provision is made for interboard condition alerts such as interrupt requests, DMA requests,
system-specific error conditions, or other specialized status conditions. Within this scheme
eight prioritized attention request levels, each with vectored response capability, are available
for user assignation.
This standard deals only with those characteristics that must be specified so as to ensure the
successful design and implementation of compatible boards and systems. Issues relating to
individual design specifications, and performance or safety requirements are not addressed.

– 6 – 10859 © ISO/IEC:1997
1.2 Features
The fundamental features offered by IEEE Std 1000 Bus are as follows:

8-bit Data Field Width
1 Megabyte Memory Address Range

4 Kilobyte I/O Address Range
Asynchronous Data Transfer
Transfer Error Signal
Multiple Masters
Eight Attention Request Lines
IEC 603-2 Connector
Single or Double Eurocard Boards and Modules
5 V, ±12 V and Standby Power Supply Distribution
Total Position Independence of Boards and Modules in Backplane
Total Inter-Board Compatibility
Total Central Processing Unit (CPU) Generic Device Family Independence
Potential 5 Megabyte per Second Data Transfers
1.3 Objects
This standard is intended to
1) define a general purpose microcomputer board interface;
2) specify those device-independent electrical, mechanical, and functional interface
parameters that must be met so as to effect unambiguous communication between system
elements and to effect physical compatibility;
3) specify the terminology and definitions related to the specification;
4) enable the interconnection of a wide variety of independently manufactured boards within
a single functional system;
5) define a standard that places the minimum number of restrictions on the performance
characteristics of boards within a conforming system;
6) allow microcomputer system users of relatively modest experience to assemble
modularly expandable computer systems with a high probability of success.
1.4 Definitions
The following general definitions apply throughout this standard. Additional detailed definitions
are given where appropriate.
1.4.1 General system terms
compatibility: The degree to which boards may be interconnected and used without
modification when designed according to the specifications contained within this standard.
interface: A shared boundary between two or more systems, or between two or more elements
within a system, through which information is conveyed.
interface system: The device-independent electrical, mechanical, and functional interface
elements required for unambiguous communication between two or more devices. Typical
elements include:
10859 © ISO/IEC:1997 – 7 –
– driver and receiver circuitry;

– signal line descriptions;
– timing and control conventions;

– communication protocols;
– functional logic circuits.
system: A set of interconnected boards that achieve a specified objective by the performance

of designated functions.
1.4.2 Signals and paths
address: The reference to a unit of data or the value represented by the address lines while
ADRSTB* is active.
addressed board: A board that recognizes its address while ADRSTB* is active.
arbitration: The means whereby masters compete for control of the bus and the process by
which a master is granted control of the bus.
backplane: A printed circuit board (pcb) on which connectors are mounted, into which boards
or plug-in units are inserted.
block transfer: A sequence of data transfers, in the same direction, that occur during a single
bus tran
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