ISO 6951:1986
(Main)Information processing - Processor system bus interface (Eurobus A)
Information processing - Processor system bus interface (Eurobus A)
Provides a processor system bus interface known as Eurobus A being one of a family of interfaces for modular data acquisition, processing communication and control systems for military, industrial and other applications.
General Information
Standards Content (Sample)
Foreword
ISO (the International Organization for Standardization) is a worldwide federation of
national Standards bodies (ISO member bodies). The work of preparing International
Standards is normally carried out through ISO technical committees. Esch member
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Draft International Standards adopted by the technical committees are circulated to
the member bodies for approval before their acceptance as International Standards by
the ISO Council. They are approved in accordance with ISO procedures requiring at
least 75 % approval by the member bodies voting.
International Standard ISO 6951 was prepared by Technical Committee ISO/TC 97,
Information processing s ystems.
Users should note that all’ International Standards undergo revision from time to time
and that any reference made herein to any other International Standard implies its
latest edition, unless othetwise stated.
International Organkation for Standardkation, 1986
Printed in Switzerland
ii
ISO 6951-1986 (El
Contents Page
0 Introduction .
1 Scope and field of application .
2 Definitions. . 3
3 Designation of a particular Eurobus .
4 Compliance .
5 Protocols for Eurobus A .
6 Electrical and timing requirements . 11
Annexes
................................... 20
A Eurobus lO/A logical implementation
................................... 20
B Eurobus 18/A logical implementation
...................................
C Eurobus 26/A logical implementation
...................................
D Eurobus 34/A logical implementation
.................................................
E Connector allocation
................................
F Examples of application of protocol rules
.......................
G Method of address allocation for mixed data widths
.............................
H Example of Eurobus backplane construction
........ 43
: Forced air convection cooled double Eurocard
J Mechanical Option 1
......................................................
K Extenderpanel
..............
L Examples of the application of Eurobus A timing requirements
.......................................
M Bus receiver a.c. noise rejection
........
N Test circuit and waveform for determination of transient sink current
...............................................
P Publications referred to
. . .
Ill
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INTERNATIONAL STANDARD
ISO 6951-1986 (E)
Information processing - Processor System bus interface
(Eurobus A)
The full addressing capability of the bus enables devices
0. lntroduction
to address any 8-bit byte of any word in a normal address
0.1 General. This Standard specifies the set of Signal lines
space defined by both of the following.
that constitute the bus itself, and the interfacing of devices
connected to the bus. (a) The addressing range determined by the number
of data/address bits.
This Standard specifies protocols for the allocation of bus
time to devices wishing to make transfers and for the (b) A two-bit extension to the foregoing (a). The full
transfer of data between devices. The Standard does two-bit extension is available on buses with non-shared
not, however, specify priority rules, these being left to width, but on shared-width buses the use of these bits
be formulated individually for each System. is restricted.
This Standard specifies a full set of signalling rules to be In addition, any complete word tan be addressed in a
followed by the device responsible for bus allocation and second address space of equal magnitude to the first,
by devices conducting transfers. Annex F gives illustrative designated the pseudo address space.
examples of each of the possible types of transfer.
0.3 Devices. Free choice is available to the System designer
The’set of electrical and Signal timing requirements as to the devices connected to a Eurobus and the Order in
specified in clause 6 uniquely defines the interface that
which they are connected. However, each bus needs to
is Eurobus A. Certain mechanical requirements are specified include both:
in clause 6, namely those that directly affect the electrical
(a) an arbiter, the purpose of which is to control the
characteristics (e.g. the physical length of the bus,
timedivision multiplexing of transfers on the bus;
the spacing of device connectors on the bus, the pin pitch
(b) if communication with other buses is required, a
on connectors and the Signal disposition on the connectors),
bus link to each of the other buses.
but this Standard does not further specify the mechanical
Figure 1 Shows an example of a bus with a number of
implementation. An example of a possible mechanical
typical devices including an arbiter and a bus link.
implementation of Eurobus A is given in annex J.
0.4 Bus allocation. Information is transferred between
Implernentations of Eurobus A are possible with 8, 16,24,
devices on a master-and-Slave basis. A device bids for
-bit data widths and devices having different data
32,.
control of the bus by means of its starred Request line
widths tan operate on the same bus. Logical implementa-
and becomes the master device for that transfer after
tion summaries for the first four of the possible data
the arbiter has allocated the bus to it. This Standard
widths are given in annexes A to D. Annex E specifies the
specifies the protocols by which devices bid for use of
connector allocation.
the bus and by which the arbiter allocates the use of the
The group of Signal iines constituting an assembled
bus to one of them. The Standard does not, however,
Eurobus A provides the means for the transfer of binary
specify the algorithm used in making the selection,
digital information between up to 20 devices plugged into
thus the System designer is given the choice of an
the backplane of a Single equipment shelf. Devices share
allocation algorithm in Order to optimize System
the bus on a timedivision multiplex basis. The length of
Performance.
the backplane is limited to a maximum of 460 mm.
The Signal lines form an asynchronous unbalanced voltage
The protocol whereby a master device may flag an
interface capable of operating at transfer rates of up to
interrupt to the arbiter is also specified, but the
6,5 x IO6 words or bytes per second.
subsequent action by the arbiter is left to the System
designer to define.
0.5 Bus transfers. In addition to specifying the protocols
0.2 Data width and addressing capability. The data/
for the execution of Read cycles (in which the master
address width of any device using the bus is theoretically
addresses a device as Slave and reads data from it) and
unconstrained. However, the asynchronous protocols
Write cycles (in which the master transfers data to the
and addressing facilities of Eurobus A permit devices of
addressed Slave), this Standard also specifies the protocol
8, 16, 24 and 32-bit data widths to share the Same bus,
and when the bus is so shared, the maximum data width for a Vector cycle in which an address, without data,
is transferred from master to Slave.
is that of the widest device.
ISO 6951-1986 (E)
PROCESSOR DMA-PERIPHERAL
Normaily operates as As no one processor is
INTERFACE
Master device, but tan act deemed to be the Master
CONTROLLER
as Slave when in receipt device on the bus, several Controls the transfer of data
procossors may be
of interrupts. to or from a user peripheral,
connected to the Same bus. performs DMA bus transfers
as a Master device and
receives control words as a
Slave.
1 J
ARBITER
Allocates use of the bus to I
requesting Master devices. 1
I
t
t
J RECUEST LINES
BUS ‘A’
I
MEMORY MEMORY MAPPE0
BUS LINK
Blocks of memory are PERIPHERAL INTERFACE Permits information to be
normally Siave devices, i.e.
CONTROLLER transferred between the two
they respond to transfers This Slave device controls
buses to which it is
initiated by other (Master) the activity of a user
connected.
devices. peripheral.
BUS ‘B’
l
Figure 1. Eurobus with some typical devices
(c) the required characteristics of the bus transmitters
The bus allocation protocols permit a master to hold the
and receivers;
bus for repeated use without the need to make a fresh
bid for every transfer, while also giving the arbiter the
(d) the required characteristics of the spurs to be
abiiity to instruct any master to release the bus for
connected to the bus.
reallocation. A master is also permitted to retain the bus
The specified set of eiectricai characteristics presupposes
for an indivisible sequence of cycles, such as a Read-
certain bus settiing times for the transitions on the Signal
Modify-Write sequence. An additional protocoi is defined
iines. Arising from these, certain timing constraints are
whereby the arbiter may abort a cycle that is deemed to
specified. These constraints ensure that the relevant
have failed.
Signal iines will have settled to the appropriate state before
0.6 Interbus transfers. The protocols for Read, Write and
an associated control Signal transition is issued.
Vector cycles permit a master on bus A, for exampie,
0.8 Commercial and military Versions. Two Versions of
wishing to effect a transfer with a Slave on bus B,
Eurobus A are specified in this Standard, a version for a
to address a bus linker on bus A as Slave. The bus linker
commerciai temperature range (0 *C to 70 “C) and a
then bids for use of bus B as master and addresses the
Version for a military temperature range (-55 *C to
required Slave on bus B. Should master devices on both
125 “C). Where the requirements are different they are
buses attempt simultaneous transfers, the bus link cannot
separateiy specif ied for each Version.
become master on either bus and a condition of deadly
embrace ensues. The Eurobus protocois permit the
embrace to be broken simply.
The protocols used by bus links to perform interbus
1. Scope and field of application
addressing and data transfer are not within the scope
This International Standard specifies a processor System
of this Standard.
bus interface known as Eurobus A (referred to in the
0.7 Electrical requirements. The Standard specif ies the
following text as “the bus”) that is one of a family of in-
electrical and timing requirements that need to be obeyed
terfaces for use in modular data acquisition, processing
by Eurobus A devices. Aspects covered within the electrical
communication and control Systems for military, industrial
requirements include:
and other applications.
NOTE 1. More detailed information about the requirements
(a) the voltage levels of the active and quiescent logic
specified in this international Standard, including the data width
states on the bus;
and addressing capability, devices connected to the bus, bus
(b) the required characteristics of the termination
allocation, bus transfers, interbus transfers and electrical re-
networks; quirements, and background information are given in clause 0.
ISO6951-1986(E)
2.19 indivisible Operation. A sequence of bus cycles for
NOTE 2. In this International Standard, upper case letters are
used for the first letter of names of bus cycles. which the correct System function tan only be guaranteed
if no other bus cycles occur within that sequence,
NOTE 3. The titles of the publications referred to in this lnter-
national Standard are listed in annex P. e.g. a Read-Modify-Wri te sequence.
2.20 interb us transfe r. A transfe r of inf ormation between
2. Definitions
devices that uses two 0 r more bu ses and one or m ore bus
For the purposes of this International Standard the follow-
Imkers.
irig definitions apply.
2.21 interrupt. A flag passed to the arbiter by a device
2.1 address. The location of a data word, or the value on
in Order to initiate a predetermined system-dependent
the highway during the addressing phase of any Read,
function.
Write or Vector cycle.
2.22 master. The device that initiates the transfer in
2.2 arbiter. The device that performs the function of
question.
arbitration for the bus and is also responsible for servicing
2.23 normal address space. An addressing space whose
interrupts and for timing-out failed cycles and aborting
size is determined by the number of lines in the highway
them.
and that is addressable as words or bytes.
2.3 arbitration. The means whereby use of the bus is
2.24 protocol. The signalling ruies used to convey
allocated to one of the bidding devices which then becomes
information or commands between devices connected
the master.
to the bus.
2.4 backplane. The assembly of the bus with connectors
2.25 pseudo address space. A second, independent
into which spur cards may be plugged.
addressing space whose size is determined by the number
2.5 bidding device. A device that wishes to initiate a cycle of lines in the highway and that is addressable as words
or group of cycles on a bus and that requests use of the
only.
bus.
2.26 Read cycle. A bus cycle in which the master obtains
2.6 bus. complete set of bus lines used by a particular
The a word or byte from the Slave.
implerne ntati on of Eurobus.
2.27 reset. The operat io n whereby each dev ice con nected
2.7 bus cycle. A closed group of Signals on the bus that
to th e bus is put into a redetermined in itial condit ion.
P
convey information between devices connected to it.
2.28 Retain cycie. A bus cycle at the end of which the
This group consists of an addressing Phase, in which the
master keeps control of the bus in Order to complete an
master places an address on the highway for recognition
indivisible Operation.
by a Slave and, except in Vector cycles, a subsequent data
2.29 settiing time. The time taken for a bus line to settle
transfer Phase.
unambiguously into its new logical state from its previous
2.8 bus line. An electrical connection between two or
state.
more devices.
2.30 shelf. The physical structure that supports the
2.9 bus linker. A device that plugs into two or more buses
backplane an
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