ISO 21111-2:2020
(Main)Road vehicles — In-vehicle Ethernet — Part 2: Common physical entity requirements
Road vehicles — In-vehicle Ethernet — Part 2: Common physical entity requirements
This document specifies the following items to complement ISO/IEC /IEEE 8802‑3: — interface between reconciliation sublayer and physical entity including reduced gigabit media independent interface (RGMII); — common physical entity wake-up and synchronised link sleep functionalities independent from physical media and transmission bit rate. The optical and electrical component requirements and test methods for optical and electrical transmission of in-vehicle Ethernet are not in the scope of this document.
Véhicules routiers — Ethernet embarqué — Partie 2: Exigences de l’entité physique commune
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INTERNATIONAL ISO
STANDARD 21111-2
First edition
2020-10
Road vehicles — In-vehicle Ethernet —
Part 2:
Common physical entity requirements
Véhicules routiers — Ethernet embarqué —
Partie 2: Exigences de l’entité physique commune
Reference number
ISO 21111-2:2020(E)
©
ISO 2020
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ISO 21111-2:2020(E)
COPYRIGHT PROTECTED DOCUMENT
© ISO 2020
All rights reserved. Unless otherwise specified, or required in the context of its implementation, no part of this publication may
be reproduced or utilized otherwise in any form or by any means, electronic or mechanical, including photocopying, or posting
on the internet or an intranet, without prior written permission. Permission can be requested from either ISO at the address
below or ISO’s member body in the country of the requester.
ISO copyright office
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Phone: +41 22 749 01 11
Email: copyright@iso.org
Website: www.iso.org
Published in Switzerland
ii © ISO 2020 – All rights reserved
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ISO 21111-2:2020(E)
Contents Page
Foreword .iv
Introduction .v
1 Scope . 1
2 Normative references . 1
3 Terms and definitions . 1
4 Abbreviated terms . 2
5 Media independent interfaces . 2
5.1 General . 2
5.2 RGMII . 2
5.2.1 General. 2
5.2.2 RGMII signals . 3
5.2.3 Electrical signal voltage level . 6
5.2.4 Electrical signal timing . 7
5.2.5 Mapping GMII signals into RGMII electrical signals .12
6 Wake-up and synchronised link sleep functionality .13
6.1 General .13
6.2 Power state, algorithms, and service interfaces .13
6.3 Neighbour physical entities .16
6.4 Synchronised link sleep algorithm .17
6.5 Wake-up algorithm .18
6.6 Wake I/O block .18
6.7 Physical entity power state .19
6.7.1 Physical entity power state variables .19
6.8 PHY service interface .19
6.8.1 PHY_LinkSleep.request . . .19
6.8.2 PHY_LinkSleep.indication .20
6.8.3 PHY_WakeUp.request .20
6.8.4 PHY_WakeUp.indication .20
6.8.5 PHY_ConfigSleepReject.request .21
6.8.6 PHY_SleepStatus.indication .21
6.8.7 PHY_LinkSleepRequestEvent.indication .21
6.8.8 PHY_LinkSleepRequestAbort.request .22
6.9 Neighbour service interface .22
6.9.1 NPHY_WakeUpForward.request .22
6.9.2 NPHY_WakeUpForward.indication .22
6.10 Timing requirements .23
6.10.1 Synchronised link sleep algorithm timing requirements .23
6.10.2 Wake-up algorithm timing requirements .23
6.11 Quiescence current .27
Bibliography .28
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ISO 21111-2:2020(E)
Foreword
ISO (the International Organization for Standardization) is a worldwide federation of national standards
bodies (ISO member bodies). The work of preparing International Standards is normally carried out
through ISO technical committees. Each member body interested in a subject for which a technical
committee has been established has the right to be represented on that committee. International
organizations, governmental and non-governmental, in liaison with ISO, also take part in the work.
ISO collaborates closely with the International Electrotechnical Commission (IEC) on all matters of
electrotechnical standardization.
The procedures used to develop this document and those intended for its further maintenance are
described in the ISO/IEC Directives, Part 1. In particular, the different approval criteria needed for the
different types of ISO documents should be noted. This document was drafted in accordance with the
editorial rules of the ISO/IEC Directives, Part 2 (see www .iso .org/ directives).
Attention is drawn to the possibility that some of the elements of this document may be the subject of
patent rights. ISO shall not be held responsible for identifying any or all such patent rights. Details of
any patent rights identified during the development of the document will be in the Introduction and/or
on the ISO list of patent declarations received (see www .iso .org/ patents).
Any trade name used in this document is information given for the convenience of users and does not
constitute an endorsement.
For an explanation of the voluntary nature of standards, the meaning of ISO specific terms and
expressions related to conformity assessment, as well as information about ISO's adherence to the
World Trade Organization (WTO) principles in the Technical Barriers to Trade (TBT) see www .iso .org/
iso/ foreword .html.
This document was prepared by Technical Committee ISO/TC 22, Road vehicles, Subcommittee SC 31,
Data communication.
A list of all parts in the ISO 21111 series can be found on the ISO website.
Any feedback or questions on this document should be directed to the user’s national standards body. A
complete listing of these bodies can be found at www .iso .org/ members .html.
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ISO 21111-2:2020(E)
Introduction
The ISO 21111 series includes in-vehicle Ethernet requirements and test plans that are disseminated in
other International Standards and complements them with additional test methods and requirements.
The resulting requirement and test plans are structured in different documents following the Open
Systems Interconnection (OSI) reference model and grouping the documents that depend on the
physical media and bit rate used.
In general, the Ethernet requirements are specified in ISO/IEC/IEEE 8802-3. The ISO 21111 series
provides supplemental specifications (e.g. wake-up, I/O functionality), which are required for in-vehicle
Ethernet applications. In road vehicles, Ethernet networks are used for different purposes requiring
different bit-rates. Currently, the ISO 21111 series specifies the 1-Gbit/s optical and 100-Mbit/s
electrical physical layer.
The ISO 21111 series contains requirement specifications and test methods related to the in-vehicle
Ethernet. This includes requirement specifications for physical layer entity (e.g. connectors, physical
layer implementations) providers, device (e.g. electronic control units, gateway units) suppliers, and
system (e.g. network systems) designers. Additionally, there are test methods specified for conformance
testing and for interoperability testing.
Safety (electrical safety, protection, fire, etc.) and electromagnetic compatibility (EMC) requirements
are out of the scope of the ISO 21111 series.
The structure of the specifications given in the ISO 21111 series complies with the Open Systems
[1] [5]
Interconnection (OSI) reference model specified in ISO/IEC 7498-1 and ISO/IEC 10731 .
ISO 21111-1 defines the terms which are used in this series of standards and provides an overview of
the standards for in-vehicle Ethernet including the complementary relations to ISO/IEC/IEEE 8802-3,
the document structure, type of physical entities, in-vehicle Ethernet specific functionalities and so on.
ISO 21111-2 specifies the interface between reconciliation sublayer and physical entity including
reduced gigabit media independent interface (RGMII), and the common physical entity wake-up and
synchronised link sleep functionalities, independent from physical media and bit rate.
This document specifies supplemental requirements to a physical layer capable of transmitting
1-Gbit/s over plastic optical fibre compliant with ISO/IEC/IEEE 8802-3, with specific application to
communications inside road vehicles, and a test plan for physical entity conformance testing.
ISO 21111-4 specifies the optical components requirements and test methods for 1-Gbit/s optical in-
vehicle Ethernet.
ISO 21111-5 specifies, for 1-Gbit/s optical in-vehicle Ethernet, requirements on the physical layer at
system level, requirements on the interoperability test set-ups, the interoperability test plan that checks
the requirements for the physical layer at system level, requirements on the device-level physical layer
conformance test set-ups, and device-level physical layer conformance test plan that checks a set of
requirements for the OSI physical layer that are relevant for device vendors.
ISO 21111-6 specifies advanced features of an ISO/IEC/IEEE 8802-3 in-vehicle Ethernet physical layer
(often also called transceiver), e.g. for diagnostic purposes for in-vehicle Ethernet physical layers. It
specifies advanced physical layer features, wake-up and sleep features, physical layer test suite,
physical layer control requirements and conformance test plan, physical sublayers test suite and
physical sublayers requirements and conformance test plan.
ISO 21111-7 specifies the implementation for ISO/IEC/IEEE 8802-3:2017/Amd 1:2017, which defines
the interface implementation for automotive applications together with requirements on components
used to realize this Bus Interface Network (BIN). ISO 21111-7 also defines further testing and system
requirements for systems implemented according to the system specification. In addition, ISO 21111-7
defines the channels for tests of transceivers with a test wiring harness that simulates various electrical
communication channels.
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ISO 21111-2:2020(E)
ISO 21111-8 specifies the transmission media, the channel performance and the tests for
ISO/IEC/IEEE 8802-3 in-vehicle Ethernet.
ISO 21111-9 specifies the data link layer requirements and conformance test plan. It specifies the
requirements and test plan for devices and systems with bridge functionality.
ISO 21111-10 specifies the application to network layer requirements and test plan. It specifies the
requirements and test plan for devices and systems that include functionality related with OSI layers
from 3 to 7.
Figure 1 shows the parts of the ISO 21111 series and the document structure.
Figure 1 — In-vehicle Ethernet document reference according to the OSI model
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INTERNATIONAL STANDARD ISO 21111-2:2020(E)
Road vehicles — In-vehicle Ethernet —
Part 2:
Common physical entity requirements
1 Scope
This document specifies the following items to complement ISO/IEC /IEEE 8802-3:
— interface between reconciliation sublayer and physical entity including reduced gigabit media
independent interface (RGMII);
— common physical entity wake-up and synchronised link sleep functionalities independent from
physical media and transmission bit rate.
The optical and electrical component requirements and test methods for optical and electrical
transmission of in-vehicle Ethernet are not in the scope of this document.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies. For
undated references, the latest edition of the referenced document (including any amendments) applies.
ISO 21111-1, Road vehicles — In-vehicle Ethernet — Part 1: General information and definitions
JEDEC – JESD8C.01:2006, Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated Circuits
JEDEC – JESD8 -5A: 2006, 2.5 V ± 0.2 V (Normal Range) and 1.8 V – 2.7 V (Wide Range) Power Supply Voltage
and Interface Standard for Nonterminated Digital Integrated Circuits
JEDEC – JESD8 -7A: 1997, 1.8 V ± 0.15 V (Normal Range) and 1.2 V – 1.95 V (Wide Range) Power Supply
Voltage and Interface Standard for Nonterminated Digital Integrated Circuits
3 Terms and definitions
For the purposes of this document, the terms and definitions given in ISO 21111-1 and the following apply.
ISO and IEC maintain terminological databases for use in standardization at the following addresses:
— ISO Online browsing platform: available at https:// www .iso .org/ obp
— IEC Electropedia: available at http:// www .electropedia .org/
3.1
double data rate
DDR
data transmission scheme, in which the data is transferred on both the rising and falling edges of the
clock signal
3.2
event
piece of management information exchanged between a calling physical entity and a called physical
entity
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ISO 21111-2:2020(E)
4 Abbreviated terms
DoD delay on destination
DoS delay on source
GMII gigabit media independent interface
I/O input and output
MAC media access control
MDC management data clock
MDIO management data input/output
MII media independent interface
N/A not applicable
PHY physical layer
RGMII reduced gigabit media independent interface
RTBI reduced ten-bit interface
RX receiver
TX transmitter
5 Media independent interfaces
5.1 General
ISO/IEC/IEEE 8802-3 specifies several speed-specific interfaces which are recommended for the
communication between the reconciliation sub-layer and the PCS sub-layer. Two of the recommended
interfaces are MII, used for10-Mbit/s and 100-Mbit/s capable physical entities, and GMII for 1-Gbit/s
capable physical entities.
ISO/IEC/IEEE 8802-3:2017, Clause 22 specifies MII and ISO/IEC/IEEE 8802-3:2017, Clause 35
specifies GMII.
GMII signals, TXD and RXD, as specified in ISO/IEC/IEEE 8802-3:2017, Clause 35 are 8-bits wide. A
direct mapping of the TXD or RXD 8-bits wide signals of the GMII interface into eight electrical lines is
a drawback for some implementations. A mapping from GMII signals to a reduced set of electrical lines
is specified in 5.2.
5.2 RGMII
5.2.1 General
The RGMII architecture (see Figure 2) is composed by the mapping of the GMII interface into a reduced
set of signal lines, the reduced set of signal lines, and the de-mapping from the reduced set of signal
lines into the GMII interface. In this subclause RGMII signal lines are the reduced set of signal lines in
Figure 2.
The RGMII transmitter side adapter shall adapt the GMII signals to the RGMII signal lines in the
reconciliation sub-layer side. The RGMII receiver side adapter shall adapt the RGMII signal lines to the
GMII signals in the PCS sub-layer side.
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ISO 21111-2:2020(E)
5.2.2 specifies the RGMII signal lines. Each RGMII signal line is able to transmit an electrical signal.
5.2.3 specifies the RGMII electrical signal voltage levels and 5.2.4 specifies the RGMII electrical signal
timing. 5.2.5 specifies how the GMII signals shall be mapped to the RGMII signal lines and vice versa.
All signals transmitted in an electrical signal line shall be conveyed with positive logic except if it is
specified differently.
An electrical signal line shall be at logic high when it is at a voltage level greater than certain threshold.
This threshold depends on the RGMII signal line nominal voltage.
An electrical signal line shall be at logic low when it is at a voltage level lower than certain threshold.
This threshold depends on the RGMII signal line nominal voltage.
JEDEC - JESD8C.01:2006 shall be used for the thresholds for RGMII signal line voltage of 3,3 V.
JEDEC - JESD8 -5A: 2006 shall be used for the thresholds for RGMII signal line voltage of 2,5 V.
JEDEC - JESD8 -7A: 1997 shall be used for the thresholds for RGMII signal line voltage of 1,8 V.
5.2.2 RGMII signals
Figure 2 shows the architecture of the RGMII interface.
The RGMII is a full-duplex bidirectional interface and transfers data simultaneously in both directions.
The RGMII connects the upper GMII and the lower GMII interfaces by means of adapters, which convert
GMII signals to RGMII signals and vice versa.
The signals of each of the interfaces are grouped by the signal flow direction. The signals going in a
downward direction in Figure 2 compose the transmit path, and the signals going in an upward
direction compose the receive path. The transmitter side adapter is the signal source in the RGMII
transmit path and the receiver side adapter is the signal source in the RGMII receive path.
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ISO 21111-2:2020(E)
Figure 2 — RGMII architecture
Table 1 specifies the conversion of the GMII signals to the RGMII signals in the transmit path at the
transmit side. The signals in the column “RGMII adapter internal signals” are only available inside the
adapter and are used to convert the GMII signals. All GMII electrical signals are only valid during the
rising edge of the GTX_CLK signal, whereas the RGMII adapter internal signals are valid during both
edges of the A_TXC signal.
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ISO 21111-2:2020(E)
Table 1 — Conversion table for adapter at transmit side in transmit path
GMII signal RGMII adapter internal signal RGMII signal Remark
TXC rising edge TXC falling edge
GTX_CLK A_TXC TXC N/A
TX_EN A_TXEN N/A A_TXEN=TX_EN
TX_CTL
TX_ER N/A A_TXERR A_TXERR=TX_EN xor TX_ER
TXD7 N/A A_TD7 TD3 N/A
TXD6 N/A A_TD6 TD2 N/A
TXD5 N/A A_TD5 TD1 N/A
TXD4 N/A A_TD4 TD0 N/A
TXD3 A_TD3 N/A TD3 N/A
TXD2 A_TD2 N/A TD2 N/A
TXD1 A_TD1 N/A TD1 N/A
TXD0 A_TD0 N/A TD0 N/A
Table 2 specifies the conversion of the RGMII signals to GMII signals in the transmit path at the receiver
side. The signals in the column “RGMII adapter internal signal” are only available inside the adapter.
Table 2 — Conversion table for adapter at receiver side in transmit path
RGMII signal RGMII adapter internal signal GMII signal Remark
TXC rising edge TXC falling edge
TXC A_TXC GTX_CLK N/A
A_TXEN N/A TX_EN TX_EN=A_TXEN
TX_CTL
N/A A_TXERR TX_ER TX_ER=A_TXEN xor A_TXERR
TD3 A_TD3 N/A TXD3 N/A
N/A A_TD7 TXD7 N/A
TD2 A_TD2 N/A TXD2 N/A
N/A A_TD6 TXD6 N/A
TD1 A_TD1 N/A TXD1 N/A
N/A A_TD5 TXD5 N/A
TD0 A_TD0 N/A TXD0 N/A
N/A A_TD4 TXD4 N/A
Table 3 specifies the conversion of the GMII signals to RGMII signals in the receive path at the receiver
side. The signals in the column “RGMII adapter internal signal” are only available inside the adapter.
Table 3 — Conversion table for adapter at receiver side in receive path
GMII signal RGMII adapter internal signal RGMII signal Remark
TXC rising edge TXC falling edge
RX_CLK A_RXC RX_CLK N/A
RX_DV A_RXDV N/A A_RXDV=RX_DV
TX_CTL
RX_ER N/A A_RXERR A_RXERR=RX_DV xor RX_ER
RXD7 N/A A_RD7 RD3 N/A
RXD6 N/A A_RD6 RD2 N/A
RXD5 N/A A_RD5 RD1 N/A
RXD4 N/A A_RD4 RD0 N/A
RXD3 A_RD3 N/A RD3 N/A
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ISO 21111-2:2020(E)
Table 3 (continued)
GMII signal RGMII adapter internal signal RGMII signal Remark
TXC rising edge TXC falling edge
RXD2 A_RD2 N/A RD2 N/A
RXD1 A_RD1 N/A RD1 N/A
RXD0 A_RD0 N/A RD0 N/A
Table 4 specifies the conversion of the RGMII signals to GMII signals in the receive path at the transmitter
side. The signals in the column “RGMII adapter internal signal” are only available inside the adapter.
Table 4 — Conversion table for adapter at transmitter side in receive path
RGMII signal RGMII adapter internal signal GMII signal Remark
TXC rising edge TXC falling edge
RXC A_TXC GTX_CLK N/A
A_RXDV N/A RX_DV RX_DV=A_RXDV
RX_CTL
N/A A_RXERR RX_ER RX_ER=A_RXDV xor A_RXERR
RD3 A_RD3 N/A RXD3 N/A
N/A A_RD7 RXD7 N/A
RD2 A_RD2 N/A RXD2 N/A
N/A A_RD6 RXD6 N/A
RD1 A_RD1 N/A RXD1 N/A
N/A A_RD5 RXD5 N/A
RD0 A_RD0 N/A RXD0 N/A
N/A A_RD4 RXD4 N/A
5.2.3 Electrical signal voltage level
Figure 3 specifies RGMII electrical signal voltage levels.
The RGMII electrical signal nominal voltage level of a RGMII signal line shall be at least one of these
values: 1,8 V, 2,5 V or 3,3 V.
The 100 % value shown in Figure 3 is the RGMII electrical signal nominal voltage level of a RGMII signal
line. All electrical signal voltage levels in this document are scaled with the RGMII electrical signal
nominal voltage level.
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ISO 21111-2:2020(E)
Figure 3 — RGMII electrical signal voltage level
5.2.4 Electrical signal timing
5.2.4.1 Signal delay mode
The electrical signals transmitted through the RGMII signal lines use the DDR data transfer scheme.
The clock electrical signal is delayed with respect to the rest of the electrical signals transmitted in the
data interface. This delay is defined as delay mismatch.
The electrical interconnection between source and destination of TX_CTL, TX_TD0 to TX_TD3 signal
lines shall have a maximum delay mismatch of 150 ps. The electrical interconnection between source and
destination of RX_CTL, RX_RD0 to RX_RD3 signal line shall have a maximum delay mismatch of 150 ps.
Depending on the electrical signal direction specified in Table 1, the source is either the RGMII
reconciliation sub-layer side or the RGMII PCS sub-layer side, in the same way, the destination side is
either the RGMII reconciliation sub-layer side or the RGMII PCS sub-layer side.
The RGMII shall support the following two signal delay modes.
— Delay on destination (DoD): all electrical signals in the data interface are transmitted edge aligned.
The delay mismatch of the clock signal shall be accomplished by the destination side. The electrical
signal parameters in DoD mode are specified in 5.2.4.2.
— Delay on source (DoS): the source side already provides the delay mismatch of the clock signal. The
electrical signal parameters in DoS mode are specified in 5.2.4.3.
5.2.4.2 Electrical signal timing parameters in DoD mode
Figures 4 and 5, and Tables 5 and 6 define electrical signal timing in DoD mode.
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ISO 21111-2:2020(E)
Figure 4 — Electrical signal timing parameters at source side in DoD mode
Table 5 — Duty cycle and skews at source side in DoD mode
Symbol Parameter name Minimum Maximum
value value
(ns) (ns)
t clock duty cycle high minimum time 3,6 N/A
dutyHigh
t clock duty cycle low minimum time 3,6 N/A
dutyLow
t data to clock skew in DoD mode N/A 0,5
DCskewDoDTr
at signal source rising edge
t clock to data skew in DoD mode N/A 0,5
CDskewDoDTr
at signal source rising edge
t data to clock skew in DoD mode N/A 0,5
DCskewDoDTf
at signal source falling edge
t clock to data skew in DoD mode N/A 0,5
CDskewDoDTf
at signal source falling edge
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ISO 21111-2:2020(E)
Figure 5 — Electrical signal timing and skews at destination side in DoD mode
Table 6 — Duty cycle and skews at destination side in DoD mode
Symbol Parameter name Minimum Maximum
value value
(ns) (ns)
t clock duty cycle high minimum time 3,6 N/A
dutyHigh
t clock duty cycle low minimum time 3,6 N/A
dutyLow
t data to clock skew in DoD mode at signal N/A 0,65
DCskewDoDRr
destination rising edge
t clock to data skew in DoD mode at signal N/A 0,65
CDskewDoDRr
destination rising edge
t data to clock skew in DoD mode at signal N/A 0,65
DCskewDoDRf
destination falling edge
t clock to data skew in DoD mode at signal N/A 0,65
CDskewDoDRf
destination falling edge
5.2.4.3 Electrical signal timing parameters in DoS mode
Figures 6 and 7, and Tables 7 and 8 define electrical signal timing in DoS mode.
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ISO 21111-2:2020(E)
Figure 6 — Electrical signal timing parameters at source side in DoS mode
Table 7 — Duty cycle and skews at source side in DoS mode
Symbol Parameter name Minimum Maximum
value value
(ns) (ns)
t clock duty cycle high minimum time 3,6 N/A
dutyHigh
t clock duty cycle low minimum time 3,6 N/A
dutyLow
t data to clock skew in DoS mode at 1,2 N/A
DCskewDoSTr
signal source rising edge
t clock to data skew in DoS mode at 1,2 N/A
CDskewDoSTr
signal source rising edge
t data to clock skew in DoS mode at 1,2 N/A
DCskewDoSTf
signal source falling edge
t clock to data skew in DoS mode at 1,2 N/A
CDskewDoSTf
signal source falling edge
10 © ISO 2020 – All rights reserved
...
DRAFT INTERNATIONAL STANDARD
ISO/DIS 21111-2
ISO/TC 22/SC 31 Secretariat: DIN
Voting begins on: Voting terminates on:
2019-07-08 2019-09-30
Road vehicles — In-vehicle Ethernet —
Part 2:
Common physical entity requirements
Véhicules routiers — Ethernet automotive —
Partie 2: Exigences de l’entité physique commune
ICS: 43.040.10
THIS DOCUMENT IS A DRAFT CIRCULATED
FOR COMMENT AND APPROVAL. IT IS
THEREFORE SUBJECT TO CHANGE AND MAY
NOT BE REFERRED TO AS AN INTERNATIONAL
STANDARD UNTIL PUBLISHED AS SUCH.
IN ADDITION TO THEIR EVALUATION AS
BEING ACCEPTABLE FOR INDUSTRIAL,
This document is circulated as received from the committee secretariat.
TECHNOLOGICAL, COMMERCIAL AND
USER PURPOSES, DRAFT INTERNATIONAL
STANDARDS MAY ON OCCASION HAVE TO
BE CONSIDERED IN THE LIGHT OF THEIR
POTENTIAL TO BECOME STANDARDS TO
WHICH REFERENCE MAY BE MADE IN
Reference number
NATIONAL REGULATIONS.
ISO/DIS 21111-2:2019(E)
RECIPIENTS OF THIS DRAFT ARE INVITED
TO SUBMIT, WITH THEIR COMMENTS,
NOTIFICATION OF ANY RELEVANT PATENT
RIGHTS OF WHICH THEY ARE AWARE AND TO
©
PROVIDE SUPPORTING DOCUMENTATION. ISO 2019
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ISO/DIS 21111-2:2019(E)
COPYRIGHT PROTECTED DOCUMENT
© ISO 2019
All rights reserved. Unless otherwise specified, or required in the context of its implementation, no part of this publication may
be reproduced or utilized otherwise in any form or by any means, electronic or mechanical, including photocopying, or posting
on the internet or an intranet, without prior written permission. Permission can be requested from either ISO at the address
below or ISO’s member body in the country of the requester.
ISO copyright office
CP 401 • Ch. de Blandonnet 8
CH-1214 Vernier, Geneva
Phone: +41 22 749 01 11
Fax: +41 22 749 09 47
Email: copyright@iso.org
Website: www.iso.org
Published in Switzerland
ii © ISO 2019 – All rights reserved
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ISO/DIS 21111-2:2019(E)
Contents Page
Foreword .iv
Introduction .v
1 Scope . 1
2 Normative references . 1
3 Terms and definitions . 1
4 Symbols and abbreviated terms . 2
5 Media independent interfaces . 2
5.1 General . 2
5.2 RGMII . 2
5.2.1 General. 2
5.2.2 RGMII signals . 4
5.2.3 Electrical signal voltage level . 5
5.2.4 Electrical signal timing . 6
5.2.5 Mapping GMII signals into RGMII electrical signals .10
6 Wake-up and synchronized link sleep functionality.11
6.1 General .11
6.2 Power state, algorithms, and service interfaces .12
6.3 Neighbour physical entities .15
6.4 Synchronized link sleep algorithm .16
6.5 Wake-up algorithm .16
6.6 Wake I/O block .17
6.7 Physical entity power state .17
6.7.1 Physical entity power state variables .17
6.7.2 Physical entity power state diagram .18
6.8 PHY service interface .18
6.8.1 PHY_LinkSleep.request . . .18
6.8.2 PHY_LinkSleep.indication .18
6.8.3 PHY_WakeUp.request .19
6.8.4 PHY_WakeUp.indication .19
6.8.5 PHY_ConfigSleepReject.request .19
6.8.6 PHY_SleepStatus.indication .20
6.8.7 PHY_LinkSleepRequestEvent.indication .20
6.8.8 PHY_LinkSleepRequestAbort.request .20
6.9 Neighbour service interface .21
6.9.1 NPHY_WakeUpForward.request .21
6.9.2 NPHY_WakeUpForward.indication .21
6.10 Timing requirements .22
6.10.1 Synchronized link sleep algorithm timing requirements .22
6.10.2 Wake-up algorithm timing requirements .22
6.11 Quiescence Current .25
Bibliography .26
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ISO/DIS 21111-2:2019(E)
Foreword
ISO (the International Organization for Standardization) is a worldwide federation of national standards
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The committee responsible for this document is ISO/ TC 22, Road vehicles, Subcommittee SC 31, Data
communication.
A list of all parts in the ISO 21111 series can be found on the ISO website.
Any feedback or questions on this document should be directed to the user’s national standards body. A
complete listing of these bodies can be found at www .iso .org/members .html.
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ISO/DIS 21111-2:2019(E)
Introduction
In general, the Ethernet physical layer requirements are specified in ISO/IEC/IEEE 8802-3:2017. The
ISO 21111- series of standards provides supplemental specifications (e.g, wake-up, I/O
functionality), which are required for in-vehicle Ethernet applications. In road vehicles, Ethernet
networks are used for different purposes requiring different bit-rates. Currently, this standard series
specifies the 1-Gbit/s optical and 100 Mbit/s electrical physical layer.
The documents in the ISO 21111- series contain requirement specifications and test methods related
to the in-vehicle Ethernet. This includes requirement specifications for physical layer entity (e.g.
connectors, PHY implementations) providers, device (e.g. electronic control units, gateway units)
suppliers, and system (e.g. network systems) designers. Additionally, there are test methods specified
for conformance testing and for interoperability testing.
The structure of the specifications given in this series of documents complies with the Open Systems
[[1]] [[2]]
Interconnection (OSI) reference model specified in ISO/IEC 7498-1 and ISO/IEC 10731 .
ISO 21111-9 specifies the data link layer requirements and conformance test plan. The requirements
and test plan for devices and systems that include bridge functionality are specified in this document.
ISO 21111-10 specifies the application to network layer requirements and test plan. The requirements
and test plan for devices and systems that include functionality related with OSI layers from 3 to 7 are
specified in this document.
Figure 1 shows the parts of the ISO 21111 standard series and the document structure.
Figure 1 — In-vehicle Ethernet document reference according to the OSI model
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DRAFT INTERNATIONAL STANDARD ISO/DIS 21111-2:2019(E)
Road vehicles — In-vehicle Ethernet —
Part 2:
Common physical entity requirements
1 Scope
This part of ISO 21111 specifies the following items to complement ISO/IEC /IEEE 8802-3:2017.
— Interface between reconciliation sublayer and physical entity including reduced gigabit media
independent interface (RGMII).
— Common physical entity wake-up and synchronized link sleep functionalities independent from
physical media and transmission bit rate.
The optical and electrical component requirements and test methods for optical and electrical
transmission of in-vehicle Ethernet are not in the scope of this document.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies. For
undated references, the latest edition of the referenced document (including any amendments) applies.
ISO 21111-1:2019, Road vehicles — In-vehicle Ethernet — Part 1: General information and definitions
ISO/IEC 7498-1:1994, Information technology — Open Systems Interconnection — Basic Reference Model:
The Basic Model — Part 1
ISO/IEC/IEEE 8802-3:2017, Information technology — Telecommunications and information exchange
between systems — Local and metropolitan area networks — Specific requirements — Part 3: Standard
for Ethernet
ISO/IEC 10731:1994, Information technology — Open Systems Interconnection — Basic Reference Model —
Conventions for the definition of OSI services
JEDEC – JESD8C.01:2006, Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated Circuits
J E DEC – J E S D 8 -5A : 20 06 , 2.5 V ± 0.2 V (Normal Range) and 1.8 V – 2.7 V (Wide Range) Power Supply Voltage
and Interface Standard for Nonterminated Digital Integrated Circuits
J E DEC – J E S D 8 -7A : 19 97, 1.8 V ± 0.15 V (Normal Range) and 1.2 V – 1.95 V (Wide Range) Power Supply
Voltage and Interface Standard for Nonterminated Digital Integrated Circuits
3 Terms and definitions
3.1
double data rate
DDR
data transmission scheme, in which the data is transferred on both the rising and falling edges of the
clock signal
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4 Symbols and abbreviated terms
DoD delay on destination
DoS delay on source
GMII gigabit media independent interface
I/O input and output
MAC media access control
MDC management data clock
MDIO management data input/output
MII media independent interface
N/A not applicable
PHY physical layer
RGMII reduced gigabit media independent interface
RTBI reduced ten-bit interface
RX receiver
TX transmitter
5 Media independent interfaces
5.1 General
ISO/IEC/IEEE 8802-3:2017 specifies several speed-specific interfaces which are recommended for the
communication between the reconciliation sub-layer and the PCS sub-layer. Two of the recommended
interfaces are MII, used for10-Mbit/s and 100-Mbit/s capable physical entities, and GMII for 1-Gbit/s
capable physical entities.
ISO/IEC/IEEE 8802-3:2017, Clause 22 specifies MII and ISO/IEC/IEEE 8802-3:2017, Clause 35
specifies GMII.
GMII signals, TXD and RXD, as specified in ISO/IEC/IEEE 8802-3:2017, Clause 35 are 8-bits wide. A
direct mapping of the TXD or RXD 8-bits wide signals of the GMII interface into eight electrical lines is a
drawback for some implementations. A mapping from GMII signals to a reduced set of electrical lines is
specified in subclause 5.2.
5.2 RGMII
5.2.1 General
The RGMII architecture (see Figure 2) is composed by the mapping of the GMII interface into a reduced
set of signal lines, the reduced set of signal lines, and the de-mapping from the reduced set of signal
lines into the GMII interface. In this subclause RGMII signal lines are the reduced set of signal lines in
Figure 2.
The RGMII transmitter side adapter shall adapt the GMII signals in the reconciliation sub-layer side to
the RGMII signal lines. The RGMII receiver side adapter shall adapt the RGMII signal lines to the GMII
signals in the PCS sub-layer side.
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Subclause 5.2.2 specifies the RGMII signal lines. Each RGMII signal line is able to transmit an electrical
signal. Subclause 5.2.3 specifies the RGMII electrical signal voltage levels and subclause 5.2.4 specifies
the RGMII electrical signal timing. Subclause 5.2.5 specifies how the GMII signals shall be mapped to
the RGMII signal lines and vice versa.
All signals transmitted in an electrical signal line shall be conveyed with positive logic except as
specified differently.
An electrical signal line shall be at logic “high” or “1” when it is at a voltage level greater than certain
thereshold. This thereshold depends on the RGMII signal line nominal voltage.
An electrical signal line shall be at logic “low” or “0” when it is at a voltage level lower than certain
thereshold. This thereshold depends on the RGMII signal line nominal voltage.
JEDEC - JESD8C.01:2006 specifies the theresholds for RGMII signal line nominal voltage equal to 3,3 V.
JEDEC - JESD8 -5A: 2006 specifies the theresholds for RGMII signal line nominal voltage equal to 2,5 V.
JEDEC - JESD8 -7A: 1997 specifies the theresholds for RGMII signal line nominal voltage equal to 1,8 V.
Figure 2 — RGMII architecture
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5.2.2 RGMII signals
Figure 2 shows the architecture of the RGMII interface.
The RGMII is a full-duplex bidirectional interface and transfers data simultaneously in both directions.
The RGMII connects the upper GMII and the lower GMII interfaces by means of adapters, which convert
GMII signals to RGMII signals and vice versa.
The signals of each of the interfaces are grouped by the signal flow direction. The signals going in the
up to down direction in Figure 2 compose the transmit path, and the signals going in the down to up
direction compose the receive path. The transmitter side adapter is the signal source in the RGMII
transmit path and the receiver side adapter is the signal source in the RGMII receive path.
Table 1 defines the conversion of the GMII signals to the RGMII signals in the transmit path at the the
transmit side. The signals in the column “RGMII adapter internal signals” are only available inside the
adapter and are used to convert the GMII signals. All GMII electrical signals are only valid during the
rising edge of the GTX_CLK signal, whereas the RGMII adapter internal signals are valid during both
edges of the A_TXC signal.
Table 1 — Conversion table for adapter at transmit side in transmit path
GMII signal RGMII adapter internal signal RGMII signal Remark
TXC rising edge TXC falling edge
GTX_CLK A_TXC TXC N/A
TX_EN A_TXEN N/A TX_CTL A_TXEN=TX_EN
TX_ER N/A A_TXERR A_TXERR=TX_EN xor TX_ER
TXD7 N/A A_TD7 TD3 N/A
TXD6 N/A A_TD6 TD2 N/A
TXD5 N/A A_TD5 TD1 N/A
TXD4 N/A A_TD4 TD0 N/A
TXD3 A_TD3 N/A TD3 N/A
TXD2 A_TD2 N/A TD2 N/A
TXD1 A_TD1 N/A TD1 N/A
TXD0 A_TD0 N/A TD0 N/A
Table 2 defines the conversion of the RGMII signals to GMII signals in the transmit path at the receiver
side. The signals in the column “RGMII adapter internal signal” are only available inside the adapter.
Table 2 — Conversion table for adapter at receiver side in transmit path
RGMII signal RGMII adapter internal signal GMII signal Remark
TXC rising edge TXC falling edge
TXC A_TXC GTX_CLK N/A
A_TXEN N/A TX_EN TX_EN=A_TXEN
TX_CTL
N/A A_TXERR TX_ER TX_ER=A_TXEN xor A_TXERR
TD3 A_TD3 N/A TXD3 N/A
N/A A_TD7 TXD7 N/A
TD2 A_TD2 N/A TXD2 N/A
N/A A_TD6 TXD6 N/A
TD1 A_TD1 N/A TXD1 N/A
N/A A_TD5 TXD5 N/A
TD0 A_TD0 N/A TXD0 N/A
N/A A_TD4 TXD4 N/A
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Table 3 defines the conversion of the GMII signals to RGMII signals in the receive path at the receiver
side. The signals in the column “RGMII adapter internal signal” are only available inside the adapter.
Table 3 — Conversion table for adapter at receiver side in receive path
GMII signal RGMII adapter internal signal RGMII signal Remark
TXC rising edge TXC falling edge
RX_CLK A_RXC RX_CLK N/A
RX_DV A_RXDV N/A TX_CTL A_RXDV=RX_DV
RX_ER N/A A_RXERR A_RXERR=RX_DV xor RX_ER
RXD7 N/A A_RD7 RD3 N/A
RXD6 N/A A_RD6 RD2 N/A
RXD5 N/A A_RD5 RD1 N/A
RXD4 N/A A_RD4 RD0 N/A
RXD3 A_RD3 N/A RD3 N/A
RXD2 A_RD2 N/A RD2 N/A
RXD1 A_RD1 N/A RD1 N/A
RXD0 A_RD0 N/A RD0 N/A
Table 4 defines the conversion of the RGMII signals to GMII signals in the receive path at the transmitter
side. The signals in the column “RGMII adapter internal signal” are only available inside the adapter.
Table 4 — Conversion table for adapter at transmitter side in receive path
RGMII signal RGMII adapter internal signal GMII signal Remark
TXC rising edge TXC falling edge
RXC A_TXC GTX_CLK N/A
A_RXDV N/A RX_DV RX_DV=A_RXDV
RX_CTL
N/A A_RXERR RX_ER RX_ER=A_RXDV xor A_RXERR
RD3 A_RD3 N/A RXD3 N/A
N/A A_RD7 RXD7 N/A
RD2 A_RD2 N/A RXD2 N/A
N/A A_RD6 RXD6 N/A
RD1 A_RD1 N/A RXD1 N/A
N/A A_RD5 RXD5 N/A
RD0 A_RD0 N/A RXD0 N/A
N/A A_RD4 RXD4 N/A
5.2.3 Electrical signal voltage level
The RGMII electrical signal nominal voltage level of a RGMII signal line shall be at least one of these
values: 1,8 V, 2,5 V or 3,3 V
The 100 % value shown in Figure 3 is the RGMII electrical signal nominal voltage level of a RGMII signal
line. All electrical signal voltage levels in this document are scaled with the RGMII electrical signal
nominal voltage level.
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ISO/DIS 21111-2:2019(E)
Figure 3 — RGMII electrical signal voltage level
5.2.4 Electrical signal timing
5.2.4.1 Signal delay mode
The electrical signals transmitted through the RGMII signal lines use the DDR data transfer scheme. In
signal delay mode, the clock electrical signal is delayed with respect to the rest of the electrical signals
transmitted in the data interface. This delay is defined as delay mismatch.
The electrical signals transmitted through TX_CTL, TD0 to TD3 signal lines shall have a maximum delay
mismatch with respect to the TXC signal of 150 ps. The electrical signals transmitted through RX_CTL,
RD0 to RD3 signal line shall have a maximum delay mismatch with respect to the RXC signal of 150 ps.
Depending on the electrical signal direction specified in Table 1, the source is either the RGMII
reconciliation sub-layer side or the RGMII PCS sub-layer side, in the same way, the destination side is
either the RGMII reconciliation sub-layer side or the RGMII PCS sub-layer side.
The RGMII shall support the following two signal delay modes.
— Delay on destination (DoD): All electrical signals in the data interface are transmitted edge aligned.
The delay mismatch of the clock signal shall be accomplished by the destination side. The electrical
signal parameters in DoD mode are specified in subclause 5.2.4.2.
— Delay on source (DoS): The source side already provides the delay mismatch of the clock signal. The
electrical signal parameters in DoS mode are specified in subclause 5.2.4.3.
5.2.4.2 Electrical signal timing parameters in DoD mode
Figure 4 and Figure 5, Table 5 and Table 6 define electrical signal timing in DoD mode.
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Figure 4 — Electrical signal timing parameters at source side in DoD mode
Table 5 — Duty cycle and skews at source side in DoD mode
Symbol Parameter name Minimum Maximum
Value Value
ns ns
T clock duty cycle high minimum time 3,6 N/A
dutyHigh
T clock duty cycle low minimum time 3,6 N/A
dutyLow
T data to clock skew in DoD mode N/A 0,5
DCskewDoDTr
at signal source rising edge
T clock to data skew in DoD mode N/A 0,5
CDskewDoDTr
at signal source rising edge
T data to clock skew in DoD mode N/A 0,5
DCskewDoDTf
at signal source falling edge
T clock to data skew in DoD mode N/A 0,5
CDskewDoDTf
at signal source falling edge
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Figure 5 — Electrical signal timing and skews at destination side in DoD mode
Table 6 — Duty cycle and skews at destination side in DoD mode
Symbol Parameter name Minimum Maximum
Value Value
ns ns
T clock duty cycle high minimum time 3,6 N/A
dutyHigh
T clock duty cycle low minimum time 3,6 N/A
dutyLow
T data to clock skew in DoD mode at signal N/A 0,65
DCskewDoDRr
destination rising edge
T clock to data skew in DoD mode at signal N/A 0,65
CDskewDoDRr
destination rising edge
T data to clock skew in DoD mode at signal N/A 0,65
DCskewDoDRf
destination falling edge
T clock to data skew in DoD mode at signal N/A 0,65
CDskewDoDRf
destination falling edge
5.2.4.3 Electrical signal timing parameters in DoS mode
Figure 6, Figure 7 and Table 7, Table 8 define electrical signal timing in DoS mode.
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Figure 6 — Electrical signal timing parameters at source side in DoS mode
Table 7 — Duty cycle and skews at source side in DoS mode
Symbol Parameter name Minimum Maximum
Value Value
ns ns
T clock duty cycle high minimum time 3,6 N/A
dutyHigh
T clock duty cycle low minimum time 3,6 N/A
dutyLow
T data to clock skew in DoS mode at 1,2 N/A
DCskewDoSTr
signal source rising edge
T clock to data skew in DoS mode at 1,2 N/A
CDskewDoSTr
signal source rising edge
T data to clock skew in DoS mode at 1,2 N/A
DCskewDoSTf
signal source falling edge
T clock to data skew in DoS mode at 1,2 N/A
CDskewDoSTf
signal source falling edge
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Figure 7 — Electricl signal timing parameters at destination side on DoS mode
Table 8 — Duty cycle and skews at destination side in DoS mode
Symbol Parameter name Minimum Maximum
Value Value
ns ns
T clock duty cycle high minimum time 3,6 N/A
dutyHigh
T clock duty cycle low minimum time 3,6 N/A
dutyLow
T data to clock skew in DoS mode at 1,05 N/A
DCskewDoSRr
signal destination rising edge
T clock to data skew in DoS mode at 1,05 N/A
CDskewDoSRr
signal destination rising edge
T data to clock skew in DoS mode at 1,05 N/A
DCskewDoSRf
signal destination falling edge
T clock to data skew in DoS mode at 1,05 N/A
CDskewDoSRf
signal destination falling edge
5.2.4.4 General parameters
The other general RGMII parameters that shall be fulfilled are specified in Table 9.
Table 9 — General RGMII parameters
Symbol Parameter Minimum Maximum Units Remarks
value value
CloadR maximum capacitive load of signal at N/A 5 pF None
max
destination side
a
tR maximum signal rise time N/A 1 ns from 20 % to 80 %
max
a
tF maximum signal fall time N/A 1 ns from 80 % to 20 %
max
a
tR and tF are measured for a load of 5 pF at the source side.
max max
5.2.5 Mapping GMII signals into RGMII electrical signals
In this subclause the mapping of GMII signals into RGMII electrical signals that are transmitted by the
RGMII signal lines is specified. The voltage of the RGMII data and control electrical signals is sampled
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in the rising and in the falling edge of the corresponding reference clock. This technique allows that the
number of electrical lines used for transmitting the data are halved when compared with a direct GMII
mapping.
TXD<7:0>, TX_ER, TX_EN and TXC are GMII signals as defined in ISO/IEC/IEEE 8802-3:2017, clause 35.
Each of the bits that compose these signals are equal to a logical one or a logical zero that is sampled
when the TXC signal changes its logical status from logical zero to logical one.
RXD<7:0>, RX_ER, RX_DV and RXC are also GMII signals as defined in ISO/IEC/IEEE 8802-3:2017, clause
35. Each of the bits that compose these signals are equal to a logical on
...
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