iTeh StandardsiTeh Standards
EURUSD
Your shopping cart is empty.
SIST

SIST EN 123200:2001/A1:1997

(Amendment)

Sectional Specification: Single and double sided printed boards with plated-through holes

Sectional Specification: Single and double sided printed boards with plated-through holes

D97/081: CECC/SC 52 disbanded

Rahmenspezifikation: Leiterplatten mit Leiterbildern auf einer oder auf beiden Seiten mit metallisierten Löchern

Spécification intermédiaire: Cartes imprimées simples et doubles faces avec trous métallisés

Sectional specification: Single and double sided printed boards with plated-through holes - Amendment to table IV of EN

General Information

Status
Published
Publication Date
31-Jul-1997
ICS
31.180 - Printed circuits and boards
Technical Committee
ITIV - Electronics assembly technology and Environmental standardization
Current Stage
6060 - National Implementation/Publication (Adopted Project)
Start Date
01-Aug-1997
Due Date
01-Aug-1997
Completion Date
01-Aug-1997
Ref Project
EN 123200:1992/A1:1995 - Sectional Specification: Single and double sided printed boards with plated-through holes

Relations

Amends
SIST EN 123200:2001 - Sectional Specification: Single and double sided printed boards with plated-through holes
Effective Date
01-Aug-1997
Amends
SIST EN 123200:2001 - Sectional Specification: Single and double sided printed boards with plated-through holes
Effective Date
28-Jan-2023

Buy Standard

EN 123200:2001/A1:1997EN 123200:2001/A1:1997
PreviousNext
Amendment
EN 123200:2001/A1:1997
English language
5 pages
sale 10% off
Preview
sale 10% off
Preview
e-Library read for
1 day

Standards Content (Sample)

SLOVENSKI STANDARD
SIST EN 123200:2001/A1:1997
01-avgust-1997
Sectional specification: Single and double sided printed boards with plated-
through holes - Amendment to table IV of EN
Sectional Specification: Single and double sided printed boards with plated-through holes
Rahmenspezifikation: Leiterplatten mit Leiterbildern auf einer oder auf beiden Seiten mit
metallisierten Löchern
Spécification intermédiaire: Cartes imprimées simples et doubles faces avec trous
métallisés
Ta slovenski standard je istoveten z: EN 123200:1992/A1:1995
ICS:
31.180 7LVNDQDYH]MD 7,9 LQWLVNDQH Printed circuits and boards
SORãþH
SIST EN 123200:2001/A1:1997 en
2003-01.Slovenski in
...

Questions, Comments and Discussion

Ask us and Technical Secretary will try to provide an answer. You can facilitate discussion about the standard in here.

This May Also Interest You

SIST
SIST EN IEC 61249-2-51:2023(Main)
Materials for printed boards and other interconnecting structures - Part 2-51: Reinforced base materials, clad and unclad - Base materials for Integrated Circuit card carrier tape, unclad
EN IEC 61249-2-51:2023

IEC 61249-2-51:2023 specifies the construction, materials, property requirements, quality assurance, packaging, marking, storage of base materials for integrated circuit card carrier tape, unclad (hereinafter referred to as IC carrier tape base materials).
This document is applicable to IC carrier tape base materials, which is a glue-coated material, one side is woven E-glass reinforced epoxy underlayer, and the other side is coated with adhesive and protected by release film.

  • Standard
    19 pages
    English language
    sale 10% off
    e-Library read for
    1 day
  • Draft
    15 pages
    English language
    sale 10% off
    e-Library read for
    1 day
SIST
SIST EN IEC 61189-2-501:2022(Main)
Test methods for electrical materials, printed board and other interconnection structures and assemblies - Part 2-501: Test methods for materials for interconnection structures - Measurement of Resilience strength and Resilience strength Retention Factor of Flexible Dielectric Materials
EN IEC 61189-2-501:2022

This part of IEC 61189 establishes a method suitable for testing the softness of FCCL (Flexible
Copper Clad Laminate) products and related materials. This method determines the resilience
under specified conditions. The test is performed on the sample as manufactured and without
conditioning. The test does not apply to the resilience force lower than 10 mN.

  • Standard
    18 pages
    English language
    sale 10% off
    e-Library read for
    1 day
SIST
SIST EN IEC 61189-2-807:2021(Main)
Test methods for electrical materials, printed board and other interconnection structures and assemblies - Part 2-807: Test methods for materials for interconnection structures - Decomposition Temperature (Td) using TGA
EN IEC 61189-2-807:2021

This part of IEC 61189 specifies a test method to determine the decomposition temperature (Td)
of base laminate materials using thermogravimetric analysis (TGA).

  • Standard
    11 pages
    English language
    sale 10% off
    e-Library read for
    1 day
SIST
SIST EN IEC 61188-6-2:2021(Main)
Circuit boards and circuit board assemblies - Design and use - Part 6-2: Land pattern design - Description of land pattern for the most common surface mounted components (SMD)
EN IEC 61188-6-2:2021

This part of IEC 61188 describes the requirements of design and use for soldering surfaces of
land pattern on circuit boards. This document includes land pattern for surface mounted
components. These requirements are based on the solder joint requirements of
IEC 61191-2:2017.

  • Standard
    28 pages
    English language
    sale 10% off
    e-Library read for
    1 day
SIST
SIST EN IEC 61188-6-1:2021(Main)
Circuit boards and circuit board assemblies - Design and use - Part 6-1: Land pattern design - Generic requirements for land pattern on circuit boards
EN IEC 61188-6-1:2021

This part of IEC 61188 specifies the requirements for soldering surfaces on circuit boards. This
includes lands and land pattern for surface mounted components and also solderable hole
configurations for through-hole mounted components. These requirements are based on the
solder joint requirements of the IEC 61191-1, IEC 61191-2, IEC 61191-3 and IEC 61191-4.

  • Standard
    33 pages
    English language
    sale 10% off
    e-Library read for
    1 day
SIST
SIST EN IEC 62878-2-602:2021(Main)
Device Embedding assembly technology - Part 2-602: Guideline for stacked electronic module - Evaluation method of inter-module electrical connectivity
EN IEC 62878-2-602:2021

This part of IEC 62878 specifies the requirements and evaluation methods of electrical
connectivity. It is applicable to stacked electronic modules.

  • Standard
    15 pages
    English language
    sale 10% off
    e-Library read for
    1 day
SIST
SIST EN IEC 61189-5-301:2021(Main)
Test methods for electrical materials, printed boards and other interconnection structures and assemblies - Part 5-301: Test methods for printed board assemblies - Soldering paste using fine solder particles
EN IEC 61189-5-301:2021

This part of IEC 61189 specifies methods for testing the characteristics of soldering paste using
fine solder particles (hereinafter referred to as solder paste).
This document is applicable to the solder paste using fine solder particle such as type 6, type 7
specified in IEC 61190-1-2 or finer particle sizes.
This type of solder paste is used for connecting wiring and components in high-density printed
circuit boards which are used in electronic or communication equipment and such, equipping
fine wiring (e.g., minimum conductor widths and minimum conductor gaps of 60 μm or less).
Test methods for the characteristics of solder paste in this document are considering the effect
of surface activation force due to the fine sized solder particles which could affect the test result
by existing test methods.

  • Standard
    35 pages
    English language
    sale 10% off
    e-Library read for
    1 day
SIST
SIST EN IEC 62878-1:2021(Main)
Device embedding assembly technology - Part 1: Generic specification for device embedded substrates
EN IEC 62878-1:2019

IEC 62878-1:2019(E) specifies the generic requirements and test methods for device-embedded substrates. The basic test methods for printed board substrate materials and substrates themselves are specified in IEC 61189-3.
This part of IEC 62878 is applicable to device-embedded substrates fabricated by use of organic base material, which includes, for example, active or passive devices, discrete components formed in the fabrication process of electronic printed boards, and sheet-formed components.
The IEC 62878 series applies neither to the re-distribution layer (RDL) nor to electronic modules defined in IEC 62421.

  • Standard
    23 pages
    English language
    sale 10% off
    e-Library read for
    1 day
SIST
SIST EN IEC 62878-2-5:2021(Main)
Device embedded substrate - Part 2-5: Implementation of a 3D data format for device embedded substrate
EN IEC 62878-2-5:2019

IEC 62878-2-5:2019 specifies requirements based on XML schema that represents a design data format for device embedded substrate, which is a board comprising embedded active and passive devices whose electrical connections are made by means of a via, electroplating, conductive paste or printing of conductive material.
This data format is to be used for simulation (e.g. stress, thermal, EMC), tooling, manufacturing, assembly, and inspection requirements. Furthermore, the data format is used for transferring information among printed board designers, printed board simulation engineer, manufacturers, and assemblers.
IEC 62878-2-5:2019 applies to substrates using organic material. It neither applies to the re-distribution layer (RDL) nor to the electronic modules defined as M-type business model in IEC 62421.

  • Standard
    55 pages
    English language
    sale 10% off
    e-Library read for
    1 day
SIST
SIST EN IEC 61189-5-501:2021(Main)
Test methods for electrical materials, printed boards and other interconnection structures and assemblies - Part 5-501: General test methods for materials and assemblies - Surface insulation resistance (SIR) testing of solder fluxes
EN IEC 61189-5-501:2021

This part of IEC 61189 is used to quantify the deleterious effects of flux residues on surface
insulation resistance (SIR) in the presence of moisture.
Interdigitated comb patterns comprising long parallel electrodes on an IPC B53 standardized
test coupon are used for the evaluation. Coupons are conditioned and measurements taken at
a high temperature and humidity. The electrodes are electrically biased during conditioning to
facilitate electrochemical reactions, as shown in Figure 1 and Figure 3.
Reference can be made to IEC TR 61189-5-506, which examines different geometry comb
patterns: 400 μm x 500 μm; 400 μm x 200 μm; and 318 μm x 318 μm.
Specifically, this method is designed to simultaneously assess:
• leakage current caused by ionized water films and electrochemical degradation of test
vehicle, (corrosion, dendritic growth);
• provide metrics that can appropriately be used for binary classification (e.g. go/no go;
pass/fail);
• compare, rank or characterize materials and processes.
This test is carried out at high humidity and heat conditions.

  • Standard
    23 pages
    English language
    sale 10% off
    e-Library read for
    1 day