SIST-TP CEN/TR 17602-60-02:2022
(Main)Space product assurance - Techniques for radiation effects mitigation in ASICs and FPGAs handbook
Space product assurance - Techniques for radiation effects mitigation in ASICs and FPGAs handbook
This handbook provides a compilation of different techniques that can be used to mitigate the adverse effects of radiation in integrated circuits (ICs), with almost exclusive attention to Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs) to be used in space, and excluding other ICs like power devices, MMIC or sensors.
The target users of this handbook are developers and users of ICs which are meant to be used in a radiation environment. Following a bottom-up order, the techniques are presented according to the different stages of an IC development flow where they can be applied. Therefore, users of this handbook can be IC engineers involved in the selection, use or development of IC manufacturing processes, IC layouts and ASIC standard cell libraries, analogue and digital circuit designs, FPGAs, embedded memories, embedded software and the immediate electronic system (printed circuit board) containing the IC that can experience the radiation effects.
In addition, this handbook contains an overview of the space radiation environment and its effects in semiconductor devices, a section on how to validate the good implementation and effectiveness of the mitigation techniques, and a special section providing some general guidelines to help with the selection of the most adequate mitigation techniques including some examples of typical space project scenarios.
The information given in this ECSS Handbook is provided only as guidelines and for reference, and not to be used as requirements. ECSS Standards provide requirements that can be made applicable, while, ECSS Handbooks provide guidelines.
Raumfahrtproduktsicherung - Handbuch zu Minderungsmethoden von Strahlungseffekten auf ASICs und FPGAs
Ingénierie spatiale - Guide sur les techniques de durcissement des ASICs et FPGAs vis-à-vis des effets des radiations
Zagotavljanje kakovosti proizvodov v vesoljski tehniki - Priročnik za tehnike blaženja učinkov sevanja na vezja ASIC in FPGA
Ta priročnik podaja različne tehnike, ki jih je mogoče uporabiti za ublažitev škodljivih učinkov sevanja v integriranih vezjih (IC), s skoraj izključnim poudarkom na integriranih vezjih za določen namen (ASIC) in terensko programirljivih logičnih vezjih (FPGA), ki se uporabljajo v vesolju, pri čemer so izključena druga integrirana vezja, kot so omrežne naprave, mikrovalovna integrirana vezja (MMIC) ali senzorji.
Ciljni uporabniki tega priročnika so razvijalci in uporabniki integriranih vezij, namenjenih za uporabo v okolju s sevanjem. Tehnike so predstavljene v vrstnem redu od spodaj navzgor glede na različne stopnje poteka razvoja integriranih vezij, za katere jih je mogoče uporabiti. Uporabniki tega priročnika so torej lahko inženirji integriranih vezij, ki so vključeni v izbiro, uporabo ali razvoj postopkov izdelave integriranih vezij, postavitev integriranih vezij in knjižnic standardnih celic ASIC, načrtov analognih in digitalnih vezij, terensko programirljivih logičnih vezij, vgrajenih pomnilnikov, vgrajene programske opreme ter neposrednega elektronskega sistema (tiskanega vezja), ki vsebuje integrirano vezje, na katere lahko vpliva sevanje.
Ta priročnik vsebuje tudi pregled sevanja v vesoljskem okolju in njegovih učinkov v polprevodniških napravah, razdelek o tem, kako preveriti ustrezno izvajanje in učinkovitost tehnik blaženja, ter poseben razdelek, ki vsebuje nekaj splošnih smernic za pomoč pri izbiri najustreznejše tehnike blaženja, vključno z nekaterimi primeri običajnih scenarijev vesoljskih projektov.
Informacije v tem priročniku ECSS so zgolj smernice in reference ter se ne uporabljajo kot zahteve. Standardi ECSS podajajo zahteve, ki jih je mogoče uporabiti, medtem ko priročniki ECSS podajajo smernice.
General Information
Buy Standard
Standards Content (Sample)
SLOVENSKI STANDARD
SIST-TP CEN/TR 17602-60-02:2022
01-februar-2022
Zagotavljanje kakovosti proizvodov v vesoljski tehniki - Priročnik za tehnike
blaženja učinkov sevanja na vezja ASIC in FPGA
Space product assurance - Techniques for radiation effects mitigation in ASICs and
FPGAs handbook
Raumfahrtproduktsicherung - Handbuch zu Minderungsmethoden von
Strahlungseffekten auf ASICs und FPGAs
Ingénierie spatiale - Guide sur les techniques de durcissement des ASICs et FPGAs vis-
à-vis des effets des radiations
Ta slovenski standard je istoveten z: CEN/TR 17602-60-02:2021
ICS:
03.120.99 Drugi standardi v zvezi s Other standards related to
kakovostjo quality
49.140 Vesoljski sistemi in operacije Space systems and
operations
SIST-TP CEN/TR 17602-60-02:2022 en,fr,de
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.
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SIST-TP CEN/TR 17602-60-02:2022
TECHNICAL REPORT CEN/TR 17602-60-02
RAPPORT TECHNIQUE
TECHNISCHER BERICHT
December 2021
ICS 49.140
English version
Space product assurance - Techniques for radiation effects
mitigation in ASICs and FPGAs handbook
Ingénierie spatiale - Guide sur les techniques de Raumfahrtproduktsicherung - Handbuch zu
durcissement des ASICs et FPGAs vis-à-vis des effets Minderungsmethoden von Strahlungseffekten auf
des radiations ASICs und FPGAs
This Technical Report was approved by CEN on 22 November 2021. It has been drawn up by the Technical Committee
CEN/CLC/JTC 5.
CEN and CENELEC members are the national standards bodies and national electrotechnical committees of Austria, Belgium,
Bulgaria, Croatia, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy,
Latvia, Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Republic of North Macedonia, Romania, Serbia,
Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and United Kingdom.
CEN-CENELEC Management Centre:
Rue de la Science 23, B-1040 Brussels
© 2021 CEN/CENELEC All rights of exploitation in any form and by any means Ref. No. CEN/TR 17602-60-02:2021 E
reserved worldwide for CEN national Members and for
CENELEC Members.
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CEN/TR 17602-60-02:2021 (E)
Table of contents
European Foreword . 14
1 Scope . 15
2 References . 16
3 Terms, definitions and abbreviated terms . 17
3.1 Terms from other documents . 17
3.2 Terms specific to the present document . 17
3.3 Abbreviated terms. 19
4 Radiation environment and integrated circuits . 25
4.1 Overview . 25
4.2 Radiation environment in space . 25
4.3 Radiation Effects in ICs . 26
4.3.1 Overview . 26
4.3.2 Cumulative effects. 26
4.3.3 Single Event Effects (SEEs) . 27
4.3.3.1 Overview. 27
4.3.3.2 Non-destructive SEE . 28
4.3.3.3 Destructive SEE . 29
4.3.3.4 Summary . 30
5 Choosing a device hardening strategy . 31
5.1 The optimal strategy . 31
5.2 How to use this handbook . 32
6 Technology selection and process level mitigation . 35
6.1 Overview . 35
6.2 Mitigation techniques . 36
6.2.1 Epitaxial layers . 36
6.2.2 Silicon On Insulator . 37
6.2.3 Triple wells . 40
6.2.4 Buried layers . 42
6.2.5 Dry thermal oxidation . 43
6.2.6 Implantation into oxides . 45
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6.3 Technology scaling and radiation effects . 46
7 Layout . 49
7.1 Overview . 49
7.2 Mitigation techniques . 50
7.2.1 Ringed or Enclosed Layout Transistor . 50
7.2.2 Contacts and guard rings . 52
7.2.3 Dummy transistors . 55
7.2.4 Transistors Gate W/L ratio sizing . 57
8 Analogue circuits . 58
8.1 Overview . 58
Mitigation techniques . 59
8.2
8.2.1 Node Separation and Inter-digitation . 59
8.2.2 Analogue redundancy (averaging) . 63
8.2.3 Resistive decoupling . 64
8.2.4 Filtering . 67
8.2.5 Modifications in bandwidth, gain, operating speed, and current
drive . 68
8.2.6 Reduction of window of vulnerability . 71
8.2.7 Reduction of high impedance nodes . 75
8.2.8 Differential design . 77
8.2.9 Dual path hardening . 80
9 Embedded memories . 85
9.1 Overview . 85
9.2 Mitigation techniques . 86
9.2.1 Hardening of individual memory cells . 86
9.2.1.1 Overview. 86
9.2.1.2 Resistive hardening . 86
9.2.1.3 Capacitive hardening . 87
9.2.1.4 IBM hardened memory cell . 89
9.2.1.5 HIT hardened memory cell . 91
9.2.1.6 DICE hardened memory cell . 92
9.2.1.7 NASA-Whitaker hardened memory cell . 94
9.2.1.8 NASA-Liu hardened memory cell . 95
9.2.2 Bit-interleaving in memory arrays . 97
9.2.3 Data scrubbing . 99
9.3 Comparison between hardened memory cells . 100
10 Radiation-hardened ASIC libraries . 101
10.1 Introduction . 101
10.2 IMEC Design Against Radiation Effects (DARE) library . 102
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10.3 CERN 0,25 µm radiation hardened library . 103
10.4 BAE 0,15 µm radiation hardened library . 103
10.5 Ramon Chips 0,18 µm and 0,13 µm radiation hardened libraries . 103
10.6 Cobham (former Aeroflex) 600, 250, 130 and 90 nm radiation hardened
libraries . 104
10.7 Microchip Atmel MH1RT 0,35 µm and ATC18RHA 0,18 µm CMOS and
ATMX150RHA 0,15 µm SOI CMOS radiation hardened libraries . 104
10.8 ATK 0,35 µm radiation hardened cell library . 105
10.9 ST Microelectronics C65SPACE 65 nm radiation hardened library . 105
10.10 RedCat Devices radiation hardened libraries . 105
11 Digital circuits . 106
11.1 Overview . 106
11.2 Mitigation techniques . 107
11.2.1 Spatial redundancy . 107
11.2.1.1 Description of the concept . 107
11.2.1.2 Duplex architectures . 108
11.2.1.3 Triple Modular Redundancy architectures . 109
11.2.1.3.1 General . 109
11.2.1.3.2 Basic TMR . 109
11.2.1.3.3 Full TMR . 110
11.2.2 Temporal redundancy . 113
11.2.2.1 Description of the concept . 113
11.2.2.1.1 Overview . 113
11.2.2.1.2 Triple Temporal Redundancy combined with spatial redundancy 114
11.2.2.1.3 Minimal level sensitive latch . 115
11.2.3 Fail-safe, deadlock-free finite state machines . 117
11.2.4 Selective use of logic cells, clock and reset lines hardening . 121
12 System on a chip . 123
12.1 Overview . 123
12.2 Mitigation techniques . 124
12.2.1 Error Correcting Codes . 124
12.2.1.1 Introduction to multiple options . 124
12.2.1.1.1 General . 124
12.2.1.1.3 Cyclic Redundancy Check . 126
12.2.1.1.4 BCH codes . 127
12.2.1.1.5 Hamming codes . 127
12.2.1.1.6 SEC-DED codes . 128
12.2.1.1.7 Reed-Solomon codes . 128
12.2.1.1.8 Arithmetic codes . 128
12.2.1.1.9 Low Density Parity Codes . 129
12.2.2 Mitigation for Memory Blocks . 130
12.2.3 Filtering SET pulses in data paths . 131
12.2.4 Watchdog timers . 133
12.2.5 TMR in mixed-signal circuits . 135
13 Field programmable gate arrays . 138
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13.1 Overview . 138
13.2 Mitigation techniques . 140
13.2.1 Local Triple Modular Redundancy . 140
13.2.2 Global Triple Modular Redundancy . 142
13.2.3 Large grain Triple Modular Redundancy . 144
13.2.4 Embedded user memory Triple Modular Redundancy . 146
13.2.5 Additional voters in TMR data-paths to minimise DCE . 148
13.2.6 Reliability-oriented place and Route Algorithm (RoRA) . 151
13.2.7 Embedded processor protection . 153
13.2.8 Partial reconfiguration or Scrubbing of configuration memory . 155
13.2.8.1 Description of the concept . 155
13.2.8.1.1 Overview . 155
13.2.8.1.2 Full scrubbing . 156
13.2.8.1.3 Partial scrubbing . 156
13.2.8.1.4 Partial reconfiguration . 157
14 Software-implemented hardware fault tolerance . 160
14.1 Overview . 160
14.2 Mitigation techniques . 161
14.2.1 Redundancy at instruction level. 161
14.2.2 Redundancy at task level . 167
14.2.3 Redundancy at application level: using a hypervisor . 171
15 System architecture . 174
15.1 Overview . 174
15.2 Mitigation techniques . 175
15.2.1 Shielding . 175
15.2.2 Watchdog timers . 179
15.2.3 Power cycling and reset . 180
15.2.4 Latching current limiters . 180
15.2.5 Spatial Redundancy . 181
15.2.5.1 Overview. 181
15.2.5.2 Duplex architectures . 181
15.2.5.2.1 Description of the concept . 181
15.2.5.2.2 Lockstep . 182
15.2.5.2.3 Double duplex . 183
15.2.5.2.4 Double Duplex Tolerant to Transients . 183
15.2.5.3 Triple Modular Redundant system . 185
15.2.6 Error Correcting Codes . 187
15.2.7 Off-chip SET filters . 187
16 Validation methods . 188
16.1 Introduction . 188
16.2 Fault injection . 188
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16.2.1 Fault injection at transistor level . 188
16.2.1.1 Overview. 188
16.2.1.2 Physical level 2D/3D device simulation . 189
16.2.1.3 Transient fault injection simulations at electrical level . 190
16.2.2 Fault injection at gate level . 190
16.2.3 Fault injection at device level . 191
16.2.3.1 Overview. 191
16.2.3.2 Fault injection in processors . 191
16.2.3.3 Fault injection in FPGAs . 193
16.2.3.4 Analytical methods for predicting effects of soft errors on SRAM-
based FPGAs . 195
16.2.4 Fault injection at system level . 195
16.3 Real-life radiation tests . 196
16.3.1 Overview . 196
16.3.2 Tests on-board scientific satellites . 196
16.3.3 On-board stratospheric balloons . 196
16.3.4 Ground level tests . 196
16.4 Ground accelerated radiation tests . 197
16.4.1 Overview . 197
16.4.2 Standards and specifications . 197
16.4.3 SEE test methodology . 198
16.4.4 TID test methodology . 200
16.4.5 TID and SEE test facilities . 202
16.4.5.1 Overview. 202
16.4.5.2 Total ionizing dose . 203
16.4.5.3 Single event effects . 204
16.4.6 Complementary SEE test strategies . 207
16.4.6.1 Overview. 207
16.4.6.2 Laser beams SEE tests . 207
16.4.6.3 Ion-Microbeam SEE tests. 209
16.4.6.4 Californium-252 and Americium-241 SEE tests . 210
Annex A (informative) Vendor/institute-ready solutions that include
mitigation or help to mitigate . 211
Bibliography . 212
Figures
Figure 4-1: Schematic showing how galactic cosmic rays deposit energy in an
electronic device, after Lauriente and Vampola [321] . 27
Figure 4-2: Two upsets in the same word induced by a single particle (MBU) . 29
Figure 4-3: Two upsets in the different words induced by a single particle (MCU) . 29
Figure 5-1: Different abstraction levels where mitigation techniques can be applied and
naming convention for this Handbook. . 33
Figure 6-1: Example of epitaxial layer in CMOS technology . 36
6
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Figure 6-2: a) Conventional bulk NMOS transistor, b) Partially depleted SOI, c) Fully
depleted SOI . 38
Figure 6-3: a) single-well technology, b) twin-well technology, c) triple-well technology
implementing a deep n-well to isolate the p-well forming the NMOS from
the substrate . 41
Figure 6-4: Schematic view of a P-type buried layer in a P-well . 42
Figure 6-5: Radiation-induced back channel threshold voltage shifts for different SOI
substrates types, SOI layer thickness and hardening process conditions
[1] . 45
Figure 7-1: Gate oxide and STI oxide in CMOS technology . 49
Figure 7-2: a) Conventional two edge NMOS, b) Enclosed Layout Transistor NMOS . 50
Figure 7-3: Two examples of NMOS transistor layout eliminating radiation-induced
leakage current between source and drain . 51
Figure 7-4: Parasitic thyristor responsible for SEL (top), introduction of P+ guard ring
around NMOS transistor (bottom). 53
Figure 7-5: CMOS transistors with guard rings . 54
Figure 7-6: RHBD technique using dummy transistors. (a) The circuits, (b) the layouts
(layout1 on the left, layout2 on the right), after J. Chen [286]. . 56
Figure 8-1: Cross-section of two adjacent NMOS devices in a bulk CMOS technology
(From [109]) . 60
Figure 8-2: (a) Upset sensitivity data for basic DICE topology implemented in 90 nm
CMOS at three angles of incidence [114] and (b) measured upset cross-
sections as a function of azimuth angle for the Kr ion (LET of approximately
2
30 MeV*cm /mg) in improved DICE implementing nodal spacing [114] . 60
Figure 8-3: Charge collected on an adjacent transistor for a) PMOS and, b) transistors
as a function of the distance separating them ([112]) . 61
Figure 8-4: (a) Comparison of collected charge for the active and passive NMOS
devices following laser-induced charge deposition at the active device. (b)
Collected charge for passive NMOS devices verifies the charge sharing
effect and shows a nodal spacing dependence for the passive device
charge collection ([95]) . 61
Figure 8-5: Analogue averaging through the use of N identical resistors. A perturbation
(∆V) due to a particle strike on any one copy of the circuit is reduced to
∆V/N . 63
Figure 8-6: (a) A standard current-based charge pump configuration for phase-locked
loop circuits. (b) Single-event hardened voltage-based charge pump
configuration . 64
Figure 8-7: (a) A standard LC Tank Voltage-Controlled Oscillator (VCO) and (b) Single-
event hardened configuration utilizing decoupling resistor R (From
3
[118]). . 65
Figure 8-8: Brokaw bandgap reference circuit with an output low-pass filter for
improved noise, isolation, and transient suppression (From[128]). . 67
Figure 8-9: Transient PLL error response as a function of PLL bandwidth . 70
Figure 8-10: Simulated windows of vulnerability over one data conversion cycle in a 2-
bit flash ADC (From [130]). . 72
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Figure 8-11: The number of errors with respect to cycle time following laser-induced
charge deposition in a phase-locked loop (From [131]). . 72
Figure 8-12: Simulated windows of vulnerability over one data conversion cycle for un-
hardened and hardened 2-bit flash ADCs (From [132]) . 73
Figure 8-13: Simplified view of the auto-zeroed comparator (From [134] ) . 73
Figure 8-14: (a) Simplified schematic of a typical LC Tank VCO and (b) an
experimentally observed transient resulting from laser-induced charge
injection on transistor M1 (From [135]) . 75
Figure 8-15: Schematic of RHBD CMOS LC Tank VCO (From [134]) . 76
Figure 8-16: Two-dimensional slice of three PMOS transistors depicting the electrical
signal and the charge-sharing signal caused by an ion strike, i.e. pulse
quenching (From [142]). . 78
Figure 8-17: Basic differential pair . 78
Figure 8-18: Differential pair including devices A and B before and after DCC layout for
maximizing charge sharing (From [143]) . 79
Figure 8-19: Charge collected by a single transistor for single (left) and parallel (right)
transistor configuration, is shown in the top row. Differential charge is
shown in the bottom row for single (left) and parallel (right) transistor
configuration (From [143]) . 79
Figure 8-20: (a) The switched-capacitor comparator operates in two phases: (b) reset
phase and (c) evaluation phase (From [142]) . 81
Figure 8-21: Simplified circuit schematic of the differential amplifier showing the split
input paths (From [142]) . 81
Figure 8-22: The switched-capacitor comparator with split differential amplifier input
paths to harden the floating nodes against single-event upsets (From
[142]) . 82
Figure 8-23: Simulated output error voltage versus deposited charge of a sample and
hold amplifier with and without dual path har
...
SLOVENSKI STANDARD
kSIST-TP FprCEN/TR 17602-60-02:2021
01-oktober-2021
Zagotavljanje kakovosti proizvodov v vesoljski tehniki - Priročnik za tehnike
blaženja učinkov sevanja na vezja ASIC in FPGA
Space product assurance - Techniques for radiation effects mitigation in ASICs and
FPGAs handbook
Raumfahrtproduktsicherung - Handbuch zu Minderungsmethoden von
Strahlungseffekten auf ASICs und FPGAs
Ingénierie spatiale - Guide sur les techniques de durcissement des ASICs et FPGAs vis-
à-vis des effets des radiations
Ta slovenski standard je istoveten z: FprCEN/TR 17602-60-02
ICS:
03.120.99 Drugi standardi v zvezi s Other standards related to
kakovostjo quality
49.140 Vesoljski sistemi in operacije Space systems and
operations
kSIST-TP FprCEN/TR 17602-60-02:2021 en,fr,de
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.
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kSIST-TP FprCEN/TR 17602-60-02:2021
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kSIST-TP FprCEN/TR 17602-60-02:2021
TECHNICAL REPORT
FINAL DRAFT
FprCEN/TR 17602-60-02
RAPPORT TECHNIQUE
TECHNISCHER BERICHT
July 2021
ICS 49.140
English version
Space product assurance - Techniques for radiation effects
mitigation in ASICs and FPGAs handbook
Ingénierie spatiale - Guide sur les techniques de Raumfahrtproduktsicherung - Handbuch zu
durcissement des ASICs et FPGAs vis-à-vis des effets Minderungsmethoden von Strahlungseffekten auf
des radiations ASICs und FPGAs
This draft Technical Report is submitted to CEN members for Vote. It has been drawn up by the Technical Committee
CEN/CLC/JTC 5.
CEN and CENELEC members are the national standards bodies and national electrotechnical committees of Austria, Belgium,
Bulgaria, Croatia, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy,
Latvia, Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Republic of North Macedonia, Romania, Serbia,
Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and United Kingdom.
Recipients of this draft are invited to submit, with their comments, notification of any relevant patent rights of which they are
aware and to provide supporting documentation.
Warning : This document is not a Technical Report. It is distributed for review and comments. It is subject to change without
notice and shall not be referred to as a Technical Report.
CEN-CENELEC Management Centre:
Rue de la Science 23, B-1040 Brussels
© 2021 CEN/CENELEC All rights of exploitation in any form and by any means Ref. No. FprCEN/TR 17602-60-02:2021 E
reserved worldwide for CEN national Members and for
CENELEC Members.
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kSIST-TP FprCEN/TR 17602-60-02:2021
FprCEN/TR 17602-60-02:2021 (E)
Table of contents
European Foreword . 14
1 Scope . 15
2 References . 16
3 Terms, definitions and abbreviated terms . 17
3.1 Terms from other documents . 17
3.2 Terms specific to the present document . 17
3.3 Abbreviated terms. 19
4 Radiation environment and integrated circuits . 25
4.1 Overview . 25
4.2 Radiation environment in space . 25
4.3 Radiation Effects in ICs . 26
4.3.1 Overview . 26
4.3.2 Cumulative effects. 26
4.3.3 Single Event Effects (SEEs) . 27
4.3.3.1 Overview. 27
4.3.3.2 Non-destructive SEE . 28
4.3.3.3 Destructive SEE . 29
4.3.3.4 Summary . 30
5 Choosing a device hardening strategy . 31
5.1 The optimal strategy . 31
5.2 How to use this handbook . 32
6 Technology selection and process level mitigation . 35
6.1 Overview . 35
6.2 Mitigation techniques . 36
6.2.1 Epitaxial layers . 36
6.2.2 Silicon On Insulator . 37
6.2.3 Triple wells . 40
6.2.4 Buried layers . 42
6.2.5 Dry thermal oxidation . 43
6.2.6 Implantation into oxides . 45
2
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6.3 Technology scaling and radiation effects . 46
7 Layout . 49
7.1 Overview . 49
7.2 Mitigation techniques . 50
7.2.1 Ringed or Enclosed Layout Transistor . 50
7.2.2 Contacts and guard rings . 52
7.2.3 Dummy transistors . 55
7.2.4 Transistors Gate W/L ratio sizing . 57
8 Analogue circuits . 58
8.1 Overview . 58
8.2 Mitigation techniques . 59
8.2.1 Node Separation and Inter-digitation . 59
8.2.2 Analogue redundancy (averaging) . 63
8.2.3 Resistive decoupling . 64
8.2.4 Filtering . 67
8.2.5 Modifications in bandwidth, gain, operating speed, and current
drive . 68
8.2.6 Reduction of window of vulnerability . 71
8.2.7 Reduction of high impedance nodes . 75
8.2.8 Differential design . 77
8.2.9 Dual path hardening . 80
9 Embedded memories . 85
9.1 Overview . 85
9.2 Mitigation techniques . 86
9.2.1 Hardening of individual memory cells . 86
9.2.1.1 Overview. 86
9.2.1.2 Resistive hardening . 86
9.2.1.3 Capacitive hardening . 87
9.2.1.4 IBM hardened memory cell . 89
9.2.1.5 HIT hardened memory cell . 91
9.2.1.6 DICE hardened memory cell . 92
9.2.1.7 NASA-Whitaker hardened memory cell . 94
9.2.1.8 NASA-Liu hardened memory cell . 95
9.2.2 Bit-interleaving in memory arrays . 97
9.2.3 Data scrubbing . 99
9.3 Comparison between hardened memory cells . 100
10 Radiation-hardened ASIC libraries . 101
10.1 Introduction . 101
10.2 IMEC Design Against Radiation Effects (DARE) library . 102
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10.3 CERN 0,25 µm radiation hardened library . 103
10.4 BAE 0,15 µm radiation hardened library . 103
10.5 Ramon Chips 0,18 µm and 0,13 µm radiation hardened libraries . 103
10.6 Cobham (former Aeroflex) 600, 250, 130 and 90 nm radiation hardened
libraries . 104
10.7 Microchip Atmel MH1RT 0,35 µm and ATC18RHA 0,18 µm CMOS and
ATMX150RHA 0,15 µm SOI CMOS radiation hardened libraries . 104
10.8 ATK 0,35 µm radiation hardened cell library . 105
10.9 ST Microelectronics C65SPACE 65 nm radiation hardened library . 105
10.10 RedCat Devices radiation hardened libraries . 105
11 Digital circuits . 106
11.1 Overview . 106
11.2 Mitigation techniques . 107
11.2.1 Spatial redundancy . 107
11.2.1.1 Description of the concept . 107
11.2.1.2 Duplex architectures . 108
11.2.1.3 Triple Modular Redundancy architectures . 109
11.2.1.3.1 General . 109
11.2.1.3.2 Basic TMR . 109
11.2.1.3.3 Full TMR . 110
11.2.2 Temporal redundancy . 113
11.2.2.1 Description of the concept . 113
11.2.2.1.1 Overview . 113
11.2.2.1.2 Triple Temporal Redundancy combined with spatial redundancy 114
11.2.2.1.3 Minimal level sensitive latch . 115
11.2.3 Fail-safe, deadlock-free finite state machines . 117
11.2.4 Selective use of logic cells, clock and reset lines hardening . 121
12 System on a chip . 123
12.1 Overview . 123
12.2 Mitigation techniques . 124
12.2.1 Error Correcting Codes . 124
12.2.1.1 Introduction to multiple options . 124
12.2.1.1.1 General . 124
12.2.1.1.3 Cyclic Redundancy Check . 126
12.2.1.1.4 BCH codes . 127
12.2.1.1.5 Hamming codes . 127
12.2.1.1.6 SEC-DED codes . 128
12.2.1.1.7 Reed-Solomon codes . 128
12.2.1.1.8 Arithmetic codes . 128
12.2.1.1.9 Low Density Parity Codes . 129
12.2.2 Mitigation for Memory Blocks . 130
12.2.3 Filtering SET pulses in data paths . 131
12.2.4 Watchdog timers . 133
12.2.5 TMR in mixed-signal circuits . 135
13 Field programmable gate arrays . 138
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13.1 Overview . 138
13.2 Mitigation techniques . 140
13.2.1 Local Triple Modular Redundancy . 140
13.2.2 Global Triple Modular Redundancy . 142
13.2.3 Large grain Triple Modular Redundancy . 144
13.2.4 Embedded user memory Triple Modular Redundancy . 146
13.2.5 Additional voters in TMR data-paths to minimise DCE . 148
13.2.6 Reliability-oriented place and Route Algorithm (RoRA) . 151
13.2.7 Embedded processor protection . 153
13.2.8 Partial reconfiguration or Scrubbing of configuration memory . 155
13.2.8.1 Description of the concept . 155
13.2.8.1.1 Overview . 155
13.2.8.1.2 Full scrubbing . 156
13.2.8.1.3 Partial scrubbing . 156
13.2.8.1.4 Partial reconfiguration . 157
14 Software-implemented hardware fault tolerance . 160
14.1 Overview . 160
14.2 Mitigation techniques . 161
14.2.1 Redundancy at instruction level. 161
14.2.2 Redundancy at task level . 167
14.2.3 Redundancy at application level: using a hypervisor . 171
15 System architecture . 174
15.1 Overview . 174
15.2 Mitigation techniques . 175
15.2.1 Shielding . 175
15.2.2 Watchdog timers . 179
15.2.3 Power cycling and reset . 180
15.2.4 Latching current limiters . 180
15.2.5 Spatial Redundancy . 181
15.2.5.1 Overview. 181
15.2.5.2 Duplex architectures . 181
15.2.5.2.1 Description of the concept . 181
15.2.5.2.2 Lockstep . 182
15.2.5.2.3 Double duplex . 183
15.2.5.2.4 Double Duplex Tolerant to Transients . 183
15.2.5.3 Triple Modular Redundant system . 185
15.2.6 Error Correcting Codes . 187
15.2.7 Off-chip SET filters . 187
16 Validation methods . 188
16.1 Introduction . 188
16.2 Fault injection . 188
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16.2.1 Fault injection at transistor level . 188
16.2.1.1 Overview. 188
16.2.1.2 Physical level 2D/3D device simulation . 189
16.2.1.3 Transient fault injection simulations at electrical level . 190
16.2.2 Fault injection at gate level . 190
16.2.3 Fault injection at device level . 191
16.2.3.1 Overview. 191
16.2.3.2 Fault injection in processors . 191
16.2.3.3 Fault injection in FPGAs . 193
16.2.3.4 Analytical methods for predicting effects of soft errors on SRAM-
based FPGAs . 195
16.2.4 Fault injection at system level . 195
16.3 Real-life radiation tests . 196
16.3.1 Overview . 196
16.3.2 Tests on-board scientific satellites . 196
16.3.3 On-board stratospheric balloons . 196
16.3.4 Ground level tests . 196
16.4 Ground accelerated radiation tests . 197
16.4.1 Overview . 197
16.4.2 Standards and specifications . 197
16.4.3 SEE test methodology . 198
16.4.4 TID test methodology . 200
16.4.5 TID and SEE test facilities . 202
16.4.5.1 Overview. 202
16.4.5.2 Total ionizing dose . 203
16.4.5.3 Single event effects . 204
16.4.6 Complementary SEE test strategies . 207
16.4.6.1 Overview. 207
16.4.6.2 Laser beams SEE tests . 207
16.4.6.3 Ion-Microbeam SEE tests. 209
16.4.6.4 Californium-252 and Americium-241 SEE tests . 210
Annex A (informative) Vendor/institute-ready solutions that include
mitigation or help to mitigate . 211
Bibliography . 212
Figures
Figure 4-1: Schematic showing how galactic cosmic rays deposit energy in an
electronic device, after Lauriente and Vampola [321] . 27
Figure 4-2: Two upsets in the same word induced by a single particle (MBU) . 29
Figure 4-3: Two upsets in the different words induced by a single particle (MCU) . 29
Figure 5-1: Different abstraction levels where mitigation techniques can be applied and
naming convention for this Handbook. . 33
Figure 6-1: Example of epitaxial layer in CMOS technology . 36
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Figure 6-2: a) Conventional bulk NMOS transistor, b) Partially depleted SOI, c) Fully
depleted SOI . 38
Figure 6-3: a) single-well technology, b) twin-well technology, c) triple-well technology
implementing a deep n-well to isolate the p-well forming the NMOS from
the substrate . 41
Figure 6-4: Schematic view of a P-type buried layer in a P-well . 42
Figure 6-5: Radiation-induced back channel threshold voltage shifts for different SOI
substrates types, SOI layer thickness and hardening process conditions
[1] . 45
Figure 7-1: Gate oxide and STI oxide in CMOS technology . 49
Figure 7-2: a) Conventional two edge NMOS, b) Enclosed Layout Transistor NMOS . 50
Figure 7-3: Two examples of NMOS transistor layout eliminating radiation-induced
leakage current between source and drain . 51
Figure 7-4: Parasitic thyristor responsible for SEL (top), introduction of P+ guard ring
around NMOS transistor (bottom). 53
Figure 7-5: CMOS transistors with guard rings . 54
Figure 7-6: RHBD technique using dummy transistors. (a) The circuits, (b) the layouts
(layout1 on the left, layout2 on the right), after J. Chen [286]. . 56
Figure 8-1: Cross-section of two adjacent NMOS devices in a bulk CMOS technology
(From [109]) . 60
Figure 8-2: (a) Upset sensitivity data for basic DICE topology implemented in 90 nm
CMOS at three angles of incidence [114] and (b) measured upset cross-
sections as a function of azimuth angle for the Kr ion (LET of approximately
2
30 MeV*cm /mg) in improved DICE implementing nodal spacing [114] . 60
Figure 8-3: Charge collected on an adjacent transistor for a) PMOS and, b) transistors
as a function of the distance separating them ([112]) . 61
Figure 8-4: (a) Comparison of collected charge for the active and passive NMOS
devices following laser-induced charge deposition at the active device. (b)
Collected charge for passive NMOS devices verifies the charge sharing
effect and shows a nodal spacing dependence for the passive device
charge collection ([95]) . 61
Figure 8-5: Analogue averaging through the use of N identical resistors. A perturbation
(∆V) due to a particle strike on any one copy of the circuit is reduced to
∆V/N . 63
Figure 8-6: (a) A standard current-based charge pump configuration for phase-locked
loop circuits. (b) Single-event hardened voltage-based charge pump
configuration . 64
Figure 8-7: (a) A standard LC Tank Voltage-Controlled Oscillator (VCO) and (b) Single-
event hardened configuration utilizing decoupling resistor R (From
3
[118]). . 65
Figure 8-8: Brokaw bandgap reference circuit with an output low-pass filter for
improved noise, isolation, and transient suppression (From[128]). . 67
Figure 8-9: Transient PLL error response as a function of PLL bandwidth . 70
Figure 8-10: Simulated windows of vulnerability over one data conversion cycle in a 2-
bit flash ADC (From [130]). . 72
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Figure 8-11: The number of errors with respect to cycle time following laser-induced
charge deposition in a phase-locked loop (From [131]). . 72
Figure 8-12: Simulated windows of vulnerability over one data conversion cycle for un-
hardened and hardened 2-bit flash ADCs (From [132]) . 73
Figure 8-13: Simplified view of the auto-zeroed comparator (From [134] ) . 73
Figure 8-14: (a) Simplified schematic of a typical LC Tank VCO and (b) an
experimentally observed transient resulting from laser-induced charge
injection on transistor M1 (From [135]) . 75
Figure 8-15: Schematic of RHBD CMOS LC Tank VCO (From [134]) . 76
Figure 8-16: Two-dimensional slice of three PMOS transistors depicting the electrical
signal and the charge-sharing signal caused by an ion strike, i.e. pulse
quenching (From [142]). . 78
Figure 8-17: Basic differential pair . 78
Figure 8-18: Differential pair including devices A and B before and after DCC layout for
maximizing charge sharing (From [143]) . 79
Figure 8-19: Charge collected by a single transistor for single (left) and parallel (right)
transistor configuration, is shown in the top row. Differential charge is
shown in the bottom row for single (left) and parallel (right) transistor
configuration (From [143]) . 79
Figure 8-20: (a) The switched-capacitor comparator operates in two phases: (b) reset
phase and (c) evaluation phase (From [142]) . 81
Figure 8-21: Simplified circuit schematic of the differential amplifier showing the split
input paths (From [142]) .
...
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