CLC/SR 47D - Mechanical standardization of semiconductor devices
Mechanical standardization of semiconductor devices
General Information
This part of IEC 60191 gives a design guideline of open-top-type semiconductor sockets for Fine-pitch Ball Grid Array ('FBGA' hereafter) and Fine-pitch Land Grid Array ('FLGA' hereafter). This standard is intended to establish the outline drawings and dimensions of the open-top-type socket out of the test and burn-in sockets applied to FBGA and FLGA.
- Standard18 pagesEnglish languagesale 10% offe-Library read for1 day
Gives guidelines on the preparation of outline drawings of discrete devices. For preparation of outline drawings of surface mounted discrete devices, IEC 60191-6 should be referred to as well. The main changes from the previous edition are as follows: - requirement added for SI-dimensions for new drawings to be published; - former rules concerning inch-dimensions are given in an informative annex; - former rules for coding are given in an informative annex; - incorporation of the supplements; - updating of references; - restructuring and renumbering.
- Standard42 pagesEnglish languagesale 10% offe-Library read for1 day
Gives general rules for the preparation of outlines drawings of surface-mounted semiconductor devices. It supplements EN 60191-1 and 60191-3. It covers all surface-mounted discrete semiconductors devices as well as integrated circuits classified as form E.
- Standard42 pagesEnglish languagesale 10% offe-Library read for1 day
EN following parallel vote
- Amendment5 pagesEnglish languagesale 10% offe-Library read for1 day
Provides common outline drawings and dimensions for all types of structures and composed materials of fine-pitch land grid array whose terminal pitch is less than, or equal to, 0,80 mm and whose package body outline is rectangular.
- Standard23 pagesEnglish languagesale 10% offe-Library read for1 day
EN following parallel vote
- Amendment5 pagesEnglish languagesale 10% offe-Library read for1 day
Gives recommended practice for the designation of package outlines and for the classification into forms of package outlines for semiconductor devices.
- Standard22 pagesEnglish languagesale 10% offe-Library read for1 day