EN 60191-6:2004
(Main)Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages
Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages
Gives general rules for the preparation of outlines drawings of surface-mounted semiconductor devices. It supplements EN 60191-1 and 60191-3. It covers all surface-mounted discrete semiconductors devices as well as integrated circuits classified as form E.
Mechanische Normung von Halbleiterbauelementen - Teil 6: Allgemeine Regeln für die Erstellung von Gehäusezeichnungen von SMD-Halbleitergehäusen
Normalisation mécanique des dispositifs à semiconducteurs - Partie 6: Règles générales pour la préparation des dessins d'encombrement des dispositifs à semiconducteurs à montage en surface
Gives general rules for the preparation of outlines drawings of surface-mounted semiconductor devices. It supplements EN 60191-1 and 60191-3. It covers all surface-mounted discrete semiconductors devices as well as integrated circuits classified as form E.
Standardizacija mehanskih lastnosti polprevodniških elementov – 6. del: Splošna pravila za pripravo tehničnih risb okrovov površinsko nameščenih polprevodniških elementov (IEC 60191-6:2004)
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SLOVENSKI SIST EN 60191-6:2005
STANDARD
december 2005
Standardizacija mehanskih lastnosti polprevodniških elementov – 6. del:
Splošna pravila za pripravo tehničnih risb okrovov površinsko nameščenih
polprevodniških elementov (IEC 60191-6:2004)
Mechanical standardization of semiconductor devices – Part 6: General rules for
the preparation of outline drawings of surface mounted semiconductor device
packages (IEC 60191-6:2004)
ICS 01.100.25; 31.080.01; 31.240 Referenčna številka
© Standard je založil in izdal Slovenski inštitut za standardizacijo. Razmnoževanje ali kopiranje celote ali delov tega dokumenta ni dovoljeno
EUROPEAN STANDARD EN 60191-6
NORME EUROPÉENNE
EUROPÄISCHE NORM December 2004
ICS 31.080.01
English version
Mechanical standardization of semiconductor devices
Part 6: General rules for the preparation of outline drawings of surface
mounted semiconductor device packages
(IEC 60191-6:2004)
Normalisation mécanique des dispositifs Mechanische Normung von
à semiconducteurs Halbleiterbauelementen
Partie 6: Règles générales Teil 6: Allgemeine Regeln für
pour la préparation des dessins die Erstellung von Gehäusezeichnungen
d'encombrement des dispositifs von SMD-Halbleitergehäusen
à semiconducteurs à montage en surface (IEC 60191-6:2004)
(CEI 60191-6:2004)
This European Standard was approved by CENELEC on 2004-10-01. CENELEC members are bound to
comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European
Standard the status of a national standard without any alteration.
Up-to-date lists and bibliographical references concerning such national standards may be obtained on
application to the Central Secretariat or to any CENELEC member.
This European Standard exists in three official versions (English, French, German). A version in any other
language made by translation under the responsibility of a CENELEC member into its own language and
notified to the Central Secretariat has the same status as the official versions.
CENELEC members are the national electrotechnical committees of Austria, Belgium, Cyprus, Czech
Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia,
Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden,
Switzerland and United Kingdom.
CENELEC
European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung
Central Secretariat: rue de Stassart 35, B - 1050 Brussels
© 2004 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members.
Ref. No. EN 60191-6:2004 E
Foreword
The text of document 47D/584/FDIS, future edition 2 of IEC 60191-6, prepared by SC 47D,
Mechanical standardization of semiconductor devices, of IEC TC 47, Semiconductor devices, was
submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN 60191-6 on
2004-10-01.
The following dates were fixed:
– latest date by which the EN has to be implemented
at national level by publication of an identical
national standard or by endorsement (dop) 2005-07-01
– latest date by which the national standards conflicting
with the EN have to be withdrawn (dow) 2007-10-01
Annex ZA has been added by CENELEC.
__________
Endorsement notice
The text of the International Standard IEC 60191-6:2004 was approved by CENELEC as a European
Standard without any modification.
__________
- 3 - EN 60191-6:2004
Annex ZA
(normative)
Normative references to international publications
with their corresponding European publications
The following referenced documents are indispensable for the application of this document. For dated
references, only the edition cited applies. For undated references, the latest edition of the referenced
document (including any amendments) applies.
NOTE Where an international publication has been modified by common modifications, indicated by (mod), the relevant
EN/HD applies.
Publication Year Title EN/HD Year
IEC 60191-1 1966 Mechanical standardization of - -
semiconductor devices
Part 1: Preparation of drawings of
semiconductor devices
IEC 60191-3 1999 Part 3: General rules for the preparation EN 60191-3 1999
of outline drawings of integrated circuits
IEC 60191-4 1999 Part 4: Coding system and classification EN 60191-4 1999
into forms of package outlines for
semiconductor device packages
ISO 1101 1983 Technical drawings - Geometrical - -
tolerancing - Tolerancing of form,
orientation, location and run-out -
Generalities, definitions, symbols,
indications on drawings
INTERNATIONAL IEC
STANDARD 60191-6
Second edition
2004-09
Mechanical standardization
of semiconductor devices –
Part 6:
General rules for the preparation of
outline drawings of surface mounted
semiconductor device packages
IEC 2004 Copyright - all rights reserved
No part of this publication may be reproduced or utilized in any form or by any means, electronic or
mechanical, including photocopying and microfilm, without permission in writing from the publisher.
International Electrotechnical Commission, 3, rue de Varembé, PO Box 131, CH-1211 Geneva 20, Switzerland
Telephone: +41 22 919 02 11 Telefax: +41 22 919 03 00 E-mail: inmail@iec.ch Web: www.iec.ch
PRICE CODE
Commission Electrotechnique Internationale W
International Electrotechnical Commission
МеждународнаяЭлектротехническаяКомиссия
For price, see current catalogue
– 2 – 60191-6 IEC:2004(E)
CONTENTS
FOREWORD.3
1 Scope.5
2 Normative references .5
3 Definitions .5
4 Design rules .7
5 Dimensions to be specified.7
6 Notes .7
Annex A (informative) Illustration of the rules.11
A.1 Gull-wing lead package with two parallel rows of terminals (SOP,TSOP Type 2).13
A.2 Gull-wing lead package with two parallel rows of terminals (TSOP Type 1).16
A.3 Gull-wing lead package with one row of terminals on each of four sides (QFP) .19
A.4 J-bent lead package with two parallel rows of terminals (SOJ) .22
A.5 Folded lead package with one row of terminals on each of four sides (QFJ).25
A.6 Leadless package .29
A.7-1 Ball grid array package (BGA) Type 1 .32
A.7-2 Ball grid array package (BGA) Type 2 .35
Annex B (informative) Optional table format.38
Figure 1 – Illustrations of terminal projection zone .12
Figure 2 – Isometric view of an example of gauge.12
60191-6 IEC:2004(E) – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
MECHANICAL STANDARDIZATION
OF SEMICONDUCTOR DEVICES –
Part 6: General rules for the preparation of outline drawings of
surface mounted semiconductor device packages
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC
Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and non-
governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely
with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
the latter.
5) IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with an IEC Publication.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60191-6 has been prepared by subcommittee 47D: Mechanical
standardization of semiconductor devices, of IEC technical committee 47: Semiconductor
devices.
This second edition of IEC 60191-6 cancels and replaces the first edition, published in 1990
and its amendment 1 (1999), and constitutes a technical revision. This includes the following
significant changes with respect to the previous edition: improvement of the geometrical
drawing format and addition of the examples of the drawing of major packages.
– 4 – 60191-6 IEC:2004(E)
The text of this standard is based on the following documents:
FDIS Report on voting
47D/584/FDIS 47D/587/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
The committee has decided that the contents of this publication will remain unchanged until
the maintenance result date indicated on the IEC web site under "http://webstore.iec.ch" in
the data related to the specific publication. At this date, the publication will be
• reconfirmed;
• withdrawn;
• replaced by a revised edition, or
• amended.
A bilingual version of this publication may be issued at a later date.
60191-6 IEC:2004(E) – 5 –
MECHANICAL STANDARDIZATION
OF SEMICONDUCTOR DEVICES –
Part 6: General rules for the preparation of outline drawings of
surface mounted semiconductor device packages
1 Scope
This part of IEC 60191 gives general rules for the preparation of outlines drawings of surface-
mounted semiconductor devices. It supplements IEC 60191-1 and 60191-3. It covers all surface-
mounted devices-discrete semiconductors as well as integrated circuits classified as form E in
Clause 3 of IEC 60191-4.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
IEC 60191-1:1966, Mechanical standardization of semiconductor devices – Part 1: Preparation of
drawings of semiconductor devices
IEC 60191-3:1999, Mechanical standardization of semiconductor devices – Part 3: General
rules for the preparation of outline drawings of integrated circuits
IEC 60191-4:1999, Mechanical standardization of semiconductor devices – Part 4: Coding
system and classification into forms of package outlines for semiconductor devices
ISO 1101:1983, Technical drawings – Geometrical tolerancing – Tolerancing of form,
orientation, location and run-out – Generalities, definitions, symbols, indications on drawings
3 Definitions
For the purposes of this document, the following definitions apply.
3.1
seating plane
plane which designates the plane of contact of the package, including any stand-off, with the
surface on which it will be mounted
NOTE This plane is often used as the reference plane.
3.2
reference plane
plane parallel to the seating plane at a distance A3 above seating plane (does not apply to
leadless package)
...
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