IEC 61523-3:2004
(Main)Delay and power calculation standards - Part 3: Standard Delay Format (SDF) for the electronic design process
Delay and power calculation standards - Part 3: Standard Delay Format (SDF) for the electronic design process
The Standard Delay Format (SDF)is an existing OVI standard for the representation and interpretation of timing data for use at any stage of the electronic design process.The ASCII data in the SDF le is represented in a tool and language independent way and includes path delays,timing constraint values,inter-connect delays and high level technology parameters. This standard is published with a double logo IEC-IEEE. standard.
General Information
Standards Content (Sample)
INTERNATIONAL IEC
STANDARD 61523-3
First edition
2004-09
™
IEEE 1497
Delay and power calculation standards –
Part 3:
Standard Delay Format (SDF) for the
electronic design process
Reference number
IEC 61523-3(E):2004
IEEE Std. 1497(E):2001
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INTERNATIONAL IEC
STANDARD 61523-3
First edition
2004-09
™
IEEE 1497
Delay and power calculation standards –
Part 3:
Standard Delay Format (SDF) for the
electronic design process
© IEEE 2004 ⎯ Copyright - all rights reserved
IEEE is a registered trademark in the U.S. Patent & Trademark Office, owned by the Institute of Electrical and Electronics Engineers, Inc.
No part of this publication may be reproduced or utilized in any form or by any means, electronic or
mechanical, including photocopying and microfilm, without permission in writing from the publisher.
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Commission Electrotechnique Internationale
International Electrotechnical Commission
Международная Электротехническая Комиссия
– 2 –
IEEE 1497-2001(E)
CONTENTS
FOREWORD. 3
IEEE Introduction. 7
1. Overview. 8
1.1 Scope. 8
1.2 Organization of this standard . 8
2. References. 9
3. Conventions. 9
3.1 Terminology conventions. 9
3.2 Syntactic conventions. 9
4. SDF in the design process. 12
4.1 Sharing of timing data. 12
4.2 Using multiple SDF files in one design. 12
4.3 Timing data and constraints . 13
4.4 Timing environments. 13
4.5 Back-annotation of timing data for design analysis . 13
4.6 Forward-annotation of timing constraints for design synthesis. 15
4.7 Timing models supported by SDF. 16
5. Defining the standard delay format. 18
5.1 SDF file content . 18
5.2 Header section. 20
5.3 Cells . 25
5.4 Delays. 28
5.5 Timing checks. 46
5.6 Labels. 60
5.7 Timing environment. 62
Annex A (normative) Syntax of SDF . 74
Annex B (informative) SDF file examples . 84
Annex C (informative) List of Participants. 89
Published by IEC under licence from IEEE. © 2004 IEEE. All rights reserved.
– 3 –
IEEE 1497-2001(E)
INTERNATIONAL ELECTROTECHNICAL COMMISSION
___________
DELAY AND POWER CALCULATION STANDARDS –
Part 3: Standard Delay Format (SDF)
for the electronic design process
FOREWORD
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International Standard IEC/IEEE 61523-3 has been processed through IEC technical
committee 93: Design automation.
The text of this standard is based on the following documents:
IEEE Std FDIS Report on voting
1497 (2001) 93/191/FDIS 93/196/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives.
The committee has decided that the contents of this publication will remain unchanged until
2006.
IEC 61523 consists of the following parts, under the general title Delay and power
calculation standards:
IEC 61523-1, Part 1: Integrated circuit delay and power calculation systems
Published by IEC under licence from IEEE. © 2004 IEEE. All rights reserved.
– 4 –
IEEE 1497-2001(E)
IEC 61523-2, Part 2: Pre-layout delay calculation specification of CMOS ASIC libraries
IEC/IEEE 61523-3, Part 3: Standard Delay Format (SDF) for the electronic process
Published by IEC under licence from IEEE. © 2004 IEEE. All rights reserved.
– 5 –
IEEE 1497-2001(E)
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