ASTM F523-93(1997)
(Practice)Standard Practice for Unaided Visual Inspection of Polished Silicon Wafer Surfaces
Standard Practice for Unaided Visual Inspection of Polished Silicon Wafer Surfaces
SCOPE
1.1 This practice covers an inspection procedure for determining the surface quality of silicon wafers that have been polished on one side.
1.2 This practice is intended as a large-volume acceptance method and as such does not require use of a microscope or other optical instruments. Because the inspection relies on the visual acuity of the operator, test results may be very operator-sensitive. Note 1-For clarification of the identification of certain observed defects, procedures given in Practices F154 may be employed.
1.3 Defects visible to the unaided eye on polished wafer surfaces are categorized in three groups by the illumination geometry which best delineates them: front-surface high-intensity light, front-surface diffuse light, and back-surface diffuse light. These defects originate from two sources: (1) those which are caused by imperfections in the silicon crystal, and (2) those related to the manufacturing process, including handling and packaging.
1.4 The inspection described generally takes place after polishing and post-polish cleaning but before packaging. Although cleaning and packaging procedures are not a part of this practice, the inspection may be performed on a packaged product to determine the effect of such procedures on the quality of the polished wafers.
1.5 The values stated in SI units are to be regarded as the standard. The values given in parentheses are for information only.
1.6 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
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NOTICE: This standard has either been superseded and replaced by a new version or withdrawn. Contact
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Designation: F 523 – 93 (Reapproved 1997)
AMERICAN SOCIETY FOR TESTING AND MATERIALS
100 Barr Harbor Dr., West Conshohocken, PA 19428
Reprinted from the Annual Book of ASTM Standards. Copyright ASTM
Standard Practice for
Unaided Visual Inspection of Polished Silicon Wafer
Surfaces
This standard is issued under the fixed designation F 523; the number immediately following the designation indicates the year of
original adoption or, in the case of revision, the year of last revision. A number in parentheses indicates the year of last reapproval. A
superscript epsilon (e) indicates an editorial change since the last revision or reapproval.
1. Scope Structures and Contaminants Seen on Specular Silicon
Surfaces
1.1 This practice covers an inspection procedure for deter-
F 416 Test Method for Detection of Oxidation Induced
mining the surface quality of silicon wafers that have been
Defects in Polished Silicon Wafers
polished on one side.
2.2 Federal Standard:
1.2 This practice is intended as a large-volume acceptance
Fed. Std. No. 209D Clean Room and Work Station Require-
method and as such does not require use of a microscope or
ments, Controlled Environment
other optical instruments. Because the inspection relies on the
2.3 Military Standard:
visual acuity of the operator, test results may be very operator-
MIL-STD-105E Sampling Procedures and Tables for In-
sensitive.
spection by Attributes
NOTE 1—For clarification of the identification of certain observed
defects, procedures given in Practices F 154 may be employed.
3. Terminology
1.3 Defects visible to the unaided eye on polished wafer
3.1 Definitions:
surfaces are categorized in three groups by the illumination
3.1.1 back surface—of a semiconductor wafer, the exposed
geometry which best delineates them: front-surface high-
surface opposite to that upon which active semiconductor
intensity light, front-surface diffuse light, and back-surface
devices have been or will be fabricated.
diffuse light. These defects originate from two sources: (1)
3.1.2 chip—in semiconductor wafers, region where material
those which are caused by imperfections in the silicon crystal,
has been removed from the surface or edge of the wafer.
and (2) those related to the manufacturing process, including
3.1.3 contaminant, area—foreign matter that is visible to
handling and packaging.
the unaided eye under high-intensity illumination on the wafer,
1.4 The inspection described generally takes place after
of extent greater than a single light-point defect.
polishing and post-polish cleaning but before packaging. Al-
3.1.4 crack—cleavage or fracture that extends to the surface
though cleaning and packaging procedures are not a part of this
of a wafer.
practice, the inspection may be performed on a packaged
3.1.5 cratering—a surface texture of irregular closed ridges
product to determine the effect of such procedures on the
with smooth central regions.
quality of the polished wafers.
3.1.6 crow’s foot— on semiconductor wafers, intersecting
1.5 The values stated in SI units are to be regarded as the
cracks in a pattern resembling a 88crow’s foot’’ (Y)on{111}
standard. The values given in parentheses are for information
surfaces and a cross (+) on {100} surfaces.
only.
3.1.7 dimple—on semiconductor wafers, a smooth surface
1.6 This standard does not purport to address all of the
depression larger than 3 mm in diameter.
safety concerns, if any, associated with its use. It is the
3.1.8 front surface—of a semiconductor wafer, the exposed
responsibility of the user of this standard to establish appro-
surface on which active devices have been or will be fabri-
priate safety and health practices and determine the applica-
cated.
bility of regulatory limitations prior to use.
3.1.9 groove—in a semiconductor wafer, a shallow scratch
with rounded edges, that is usually the remnant of a scratch not
2. Referenced Documents
completely removed by mechanical polishing.
2.1 ASTM Standards:
3.1.10 haze—on a semiconductor wafer, a cloudy or hazy
F 154 Practices and Nomenclature for Identification of
appearance attributable to light scattering by concentrations of
microscopic surface irregularities such as pits, mounds, small
ridges or scratches, particles, etc.
This practice is under the jurisdiction of ASTM Committee F-1 on Electronics
and is the direct responsibility of Subcommittee F01.06 on Electrical and Optical
Measurement. Annual Book of ASTM Standards, Vol. 10.05.
Current edition approved Sept. 15, 1993. Published November 1993. Originally Available from Standardization Documents Order Desk, Bldg. 4 Section D, 700
published as F 523 – 77 T. Last previous edition F 523 – 88. Robbins Ave., Philadelphia, PA 19111-5094, Attn: NPODS.
NOTICE:¬This¬standard¬has¬either¬been¬superceded¬and¬replaced¬by¬a¬new¬version¬or¬discontinued.¬
Contact¬ASTM¬International¬(www.astm.org)¬for¬the¬latest¬information.¬
F 523
3.1.10.1 Discussion—The light reflection from an indi- 5. Significance and Use
vidual irregularity cannot be readily detected by the unaided
5.1 Large volumes of polished silicon wafers are produced
eye so haze is a mass effect seen as a high density of tiny
by the semiconductor industry for daily consumption in the
reflections.
production of various devices. Surface defects are frequently
3.1.11 imbedded abrasive grains—on a semiconductor wa-
deleterious to device properties.
fer, abrasive particles mechanically forced into the surface.
5.2 The defects described in this practice are visible to the
3.1.12 light point defect—an isolated, localized effect on
unaided eye under proper lighting conditions, and the inspec-
or in a wafer surface such as a particle or pit resulting in
tions are common to most consumers and producers. There-
increased light scattering intensity relative to the surrounding
fore, it is important that a uniform inspection technique be used
surface.
to aid in the manufacture of standard-quality polished silicon
3.1.13 mound—on a semiconductor wafer surface, irregu-
wafers.
larly shaped projection with one or more irregularly developed
facets.
6. Interferences
3.1.14 orange peel— on a semiconductor wafer surface,
6.1 The polished front surface of a silicon wafer can be
large-featured, roughened type of surface visible to the unaided
damaged by any one of a multitude of types of particulate
eye.
matter normally occurring in the environment. After cleaning,
3.1.15 oxide defect—an area of missing oxide on the back
polished wafers must be kept in a clean room or clean-air
side of back-sealed wafers discernible to the unaided eye.
environment at all times prior to being sealed in packaging.
3.1.16 pit—on a semiconductor wafer, a depression in the
Failure to do this can compromise the quality of a polished
surface where sloped sides of the depression meet the wafer
wafer.
surface in a distinguishable manner in contrast to the sides of
6.2 The operator in many instances is the most common
a dimple which are rounded.
source of added contamination to the wafer. Coughing, sneez-
3.1.17 saw exit mark—a ragged edge at the periphery of the
ing or even talking can be the source of additional contami-
wafer consisting of numerous small adjoining edge chips
nants. Effort must be taken to minimize the operator induced
resulting from saw blade exit.
contamination through rigorous clean room practice.
3.1.18 saw marks—surface irregularities in the form of a
6.3 Tweezers may introduce defects into the polished wafer
series of alternating ridges and depressions in arcs whose radii
surface and therefore are not suitable for use with this method.
are the same as those of the saw blade used for slicing.
NOTE 3—The recommended handling method is by means of a manu-
3.1.19 striations, n—in semiconductor technology, helical
ally vacuum pencil (see 7.5) or a robotic pickup tool. Both techniques will
features on the surface of a silicon wafer associated with local
be referred to as the pickup device in this practice.
variations in impurity concentration.
NOTE 4—Caution: During the front-surface inspection using intense
3.1.19.1 Discussion—Such variations are ascribed to peri-
light, any light reflected by the specimen or surroundings that is permitted
odic dopant-incorporation differences occurring at the rotating
to enter the operator’s eyes will greatly reduce the operator’s visual acuity
solid-liquid interface during crystal growth. These features are
and effectiveness of inspection and may cause injury to the eye.
visible to the unaided eye after preferential etching and appear
6.4 Improper cleaning and packaging methods following
to be continuous under 1003 magnification.
this inspection can compromise otherwise acceptable polished
NOTE 2—Further discussion of striations may be found in Test Method wafers.
F 416.
NOTE 5—It is suggested that the supplier periodically sample his
3.2 Other defect-related terminology, together with illustra-
packaged product to determine that packaging is not degrading the
tions of defects, may be found in Practices F 154. polished slices.
7. Apparatus
4. Summary of Practice
7.1 High-intensity Light Source— quartz halogen lamp
4.1 The polished surface is first illuminated with a high-
with collimated beam intensity greater than 230 klx (22 000
intensity source of light positioned so that the light beam is
fc).
normal to the surface. With the background illumination at a
specified low level, the surface is observed at an oblique angle.
NOTE 6—Some standard 35-mm slide projectors meet these require-
Under this viewing condition, defects that act as light-
ments.
scattering points are detected.
7.2 Clean-Air Hood located in a clean room environment
4.2 Next, the polished surface is illuminated with a large-
consistent with the particle levels being inspected on the
area diffuse light source. With the same low level of back-
wafers. The inspection area should have an ambient light level
ground illumination, the surface is again observed at an oblique
of 50 to 650 lx (5 to 60 fc) 230 mm (9 in.) from the front edge
angle. Under this viewing condition, defects larger than those
of the hood.
observable under intense collimated light are detected.
4.3 Finally, the wafer is turned over and the back side
inspected for the presence of large-area defects
...
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