ASTM F1771-97(2002)

Standard Test Method for Evaluating Gate Oxide Integrity by Voltage Ramp Technique (Withdrawn 2003)

SCOPE
This standard was transferred to SEMI (www.semi.org) May 2003
1.1 The techniques outlined in this standard are for the purpose of standardizing the procedure of measurement, analysis, and reporting of oxide integrity data between interested parties. This test method makes no representation regarding actual device failure rates or acceptance/rejection criteria. While some suggestions for data analysis are included in later sections of this test method, interpretation of results is beyond the scope of this standard. Any such interpretations should be agreed upon between interested parties prior to testing. For example, a variety of failure criteria are included to permit separation of so-called intrinsic and extrinsic oxide failures.
1.2 This test method covers the procedure for gaging the electrical strength of silicon dioxide thin films with thicknesses ranging from approximately 3 nm to 50 nm. In the analysis of films of 4 nm or less, the impact of direct tunneling on the current-voltage characteristics, and hence the specified failure criteria defined in 5.4, must be taken into account. Since oxide integrity strongly depends on wafer defects, contamination, cleanliness, as well as processing, the users of this test method are expected to include wafer manufacturers and device manufacturers.
1.3 This test method is not structure specific, but notes regarding options for different structures may be found in the appendix. The three most likely structures are simple planar metal-oxide semiconductor (MOS-capacitors) (fabricated or mercury probe), various isolation structures (for example, local oxidation of silicon (LOCOS)), and field effect transistors. This test method assumes that a low resistance ohmic contact is made to the backside of each wafer in each case. For a more detailed discussion of the design and evaluation of test structures for this test method, the reader is referred to the EIA/JEDEC Standard 35-1.
1.4 Failure criteria specified in this test method include both the fixed current limit (soft) and destructive (hard) types. In the past, use of a fixed current limit of 1 µA or more virtually ensured measurement of hard failure, as the thicker, more heavily contaminated oxides of those days typically failed catastrophically as soon as measurable currents were passed. The cleaner processing of thinner oxides now means that oxides will sustain relatively large currents with little or no evidence of failure. While use of fixed current limit testing may still be of value for assessing uniformity issues, it is widely felt that failure to continue oxide breakdown testing to the point of catastrophic oxide failure may mask the presence of defect tails, which are of critical importance in assessing long-term oxide reliability. For this reason, this test method makes provision for use of fixed limit failure criteria if desired and agreed upon by the parties to the testing, but specifies that testing be continued until hard failure is sensed.
1.5 This test method specifically does not include measurement of a charge-to-breakdown (Qbd) parameter. Industry experience with this parameter measured in a ramp-to-failure test such as this indicates that Qbd values so obtained may be unreliable indicators of oxide quality. This is because a large fraction of the value determined is collected in the last steps of the test, and the result is subject to large deviations. Qbd should be measured in a constant current or bounded current ramp test.
1.6 This test method is applicable to both n-type and p-type wafers, polished or having an epitaxial layer. In wafers with epitaxial layers, the conductivity type of the layer should be the same as that of the bulk wafer. While not excluding depletion polarity, it is preferred that measurement polarity should be in accumulation to avoid the complication of a voltage drop across the depletion layer.
1.7 While this test method is primarily intended for use in char...

General Information

• Status: Withdrawn
• Publication Date: 09-Feb-1997
• Withdrawal Date: 09-May-2003
• ICS: 29.045 - Semiconducting materials
• Technical Committee: F01 - Electronics

Relations

• Replaces: ASTM F1771-97 - Standard Test Method for Evaluating Gate Oxide Integrity by Voltage Ramp Technique
• Effective Date: 10-Feb-1997

Standards Content (Sample)

NOTICE: This standard has either been superceded and replaced by a new version or discontinued.
Contact ASTM International (www.astm.org) for the latest information.
Designation: F 1771 – 97 (Reapproved 2002)
Standard Test Method for
Evaluating Gate Oxide Integrity by Voltage Ramp
Technique
This standard is issued under the fixed designation F 1771; the number immediately following the designation indicates the year of
original adoption or, in the case of revision, the year of last revision. A number in parentheses indicates the year of last reapproval. A
superscript epsilon (e) indicates an editorial change since the last revision or reapproval.
1. Scope ensured measurement of hard failure, as the thicker, more
heavily contaminated oxides of those days typically failed
1.1 The techniques outlined in this standard are for the
catastrophically as soon as measurable currents were passed.
purpose of standardizing the procedure of measurement, analy-
The cleaner processing of thinner oxides now means that
sis, and reporting of oxide integrity data between interested
oxides will sustain relatively large currents with little or no
parties. This test method makes no representation regarding
evidence of failure. While use of fixed current limit testing may
actual device failure rates or acceptance/rejection criteria.
still be of value for assessing uniformity issues, it is widely felt
While some suggestions for data analysis are included in later
that failure to continue oxide breakdown testing to the point of
sections of this test method, interpretation of results is beyond
catastrophic oxide failure may mask the presence of defect
the scope of this standard. Any such interpretations should be
tails, which are of critical importance in assessing long-term
agreed upon between interested parties prior to testing. For
oxide reliability. For this reason, this test method makes
example, a variety of failure criteria are included to permit
provision for use of fixed limit failure criteria if desired and
separation of so-called intrinsic and extrinsic oxide failures.
agreed upon by the parties to the testing, but specifies that
1.2 This test method covers the procedure for gaging the
testing be continued until hard failure is sensed.
electrical strength of silicon dioxide thin films with thicknesses
1.5 This test method specifically does not include measure-
ranging from approximately 3 nm to 50 nm. In the analysis of
ment of a charge-to-breakdown (Q ) parameter. Industry
bd
films of 4 nm or less, the impact of direct tunneling on the
experience with this parameter measured in a ramp-to-failure
current-voltage characteristics, and hence the specified failure
test such as this indicates that Q values so obtained may be
bd
criteria defined in 5.4, must be taken into account. Since oxide
unreliable indicators of oxide quality. This is because a large
integrity strongly depends on wafer defects, contamination,
fraction of the value determined is collected in the last steps of
cleanliness, as well as processing, the users of this test method
the test, and the result is subject to large deviations. Q should
bd
are expected to include wafer manufacturers and device
be measured in a constant current or bounded current ramp test.
manufacturers.
1.6 This test method is applicable to both n-type and p-type
1.3 This test method is not structure specific, but notes
wafers, polished or having an epitaxial layer. In wafers with
regarding options for different structures may be found in the
epitaxial layers, the conductivity type of the layer should be the
appendix. The three most likely structures are simple planar
same as that of the bulk wafer. While not excluding depletion
metal-oxide semiconductor (MOS-capacitors) (fabricated or
polarity, it is preferred that measurement polarity should be in
mercury probe), various isolation structures (for example, local
accumulation to void the complication of a voltage drop across
oxidation of silicon (LOCOS)), and field effect transistors. This
the depletion layer.
test method assumes that a low resistance ohmic contact is
1.7 While this test method is primarily intended for use in
made to the backside of each wafer in each case. For a more
characterizing the SiO -silicon systems as stated above, it may
detailed discussion of the design and evaluation of test struc-
be applied in general terms to the measurement of other
tures for this test method, the reader is referred to the
metal-insulator-semiconductor structures if appropriate consid-
EIA/JEDEC Standard 35-1.
eration of the characteristics of the other materials is made.
1.4 Failure criteria specified in this test method include both
1.8 Measurement conditions specified in this test method
the fixed current limit (soft) and destructive (hard) types. In the
are conservative, intended for thorough analysis of high quality
past, use of a fixed current limit of 1 μA or more virtually
oxide-silicon systems, and to provide a regime in which new
users may safely begin testing without encountering undue
experimental artifacts. It is recognized that some experienced
This test method is under the jurisdiction of ASTM Committee F01 on
users may be working in applications where less precise data is
Electronics and is the direct responsibility of Subcommittee F01.06 on Silicon
required and a more rapid test is desirable. An example of this
Materials and Process Control.
situation is the evaluation of silicon wafer quality, where a
Current edition approved Feb. 10, 1997. Published August 1997.
Available from Electronic Industries Assoc., Washington, DC. staircase voltage step providing 0.5 MV/cm oxide field
Copyright © ASTM International, 100 Barr Harbor Drive, PO Box C700, West Conshohocken, PA 19428-2959, United States.
NOTICE: This standard has either been superceded and replaced by a new version or discontinued.
Contact ASTM International (www.astm.org) for the latest information.
F 1771 – 97 (2002)
strength resolution and a voltage step duration of 0.2 s has been 4. Summary of Test Method
used. Such test conditions may be specified when agreed upon
4.1 Overview—This is a voltage ramp test. It is most useful
as adequate by all participants to the testing. Because the
in determining changes in a given process. It is intended to be
dependence of measured parameters upon test conditions may
applied to arrays of similar capacitors on a silicon wafer or
increase as these conditions depart from those specified in this
group of wafers representing a process condition specified by
test method, it is important that all parties to these tests use the
the user. Following an optional pretest of capacitor leakage, the
same set of test conditions, so that their results will be
voltage applied to the capacitor under test is increased linearly
comparable.
with time at a specified rate, with measurements of current
1.9 This standard does not purport to address all of the
made at intervals that must correspond to oxide electric field
safety concerns, if any, associated with its use. It is the
changes less than a maximum specified value. The voltage
responsibility of the user of this standard to establish appro-
ramp continues until hard failure (destructive breakdown), as
priate safety and health practices and determine the applica-
defined by one of several specified failure criteria, is sensed.
bility of regulatory limitations prior to use.
During the measurement cycle, soft failures corresponding to
predetermined current levels are sensed and stored. At the end
2. Referenced Documents
of the measurement of this unit, hard and soft failure conditions
2.1 EIA/JEDEC Standards:
are stored for that unit, along with the appropriate hard failure
Standard 35, Procedure for the Wafer-Level Testing of Thin
2 criterion. After hard failure is detected or when the upper
Dielectrics
voltage limit of the test is reached, a post-test is performed to
Standard 35-1, General Guidelines for Designing Test
2 evaluate hard failure by sensing current at a low voltage. The
Structures for the Wafer-Level Testing of Thin Dielectrics
test cycle is then repeated for the next capacitor in the array,
Standard 35-2, Test Criteria for the Wafer-Level Testing of
2 and this is continued until all units in the specified group have
Thin Dielectrics
been tested. When testing is complete, calculations and catego-
3. Terminology
rizing of data is done as described in Sections 10, 11, and a
report of the results is generated.
3.1 Definitions:
3.1.1 hard failure—destructive failure of an MOS capacitor 4.2 Voltage Ramp—While this test can, and might best be
associated with rupture of the oxide film. done using a true linear voltage ramp, constraints of the
3.1.1.1 Discussion—This is sensed by an abrupt, irrevers- automated test equipment most often used in its performance
ible change in the current-voltage characteristics of the capaci- lead to widespread use of a staircase of voltage steps to
tor. In this test method, hard failure is determined by a
simulate the ramp. The ramp rate is specified in terms of the
relatively large change in dc conduction level between voltage rate of increase of the oxide electric field, 1.0 6 0.1 mV/cm/s.
steps, or as a change in the logarithmic slope of the current
Other ramp rates may be used if it can be shown that it does not
density-voltage characteristic. Hard failure conditions for this
affect the results, or if it is agreed upon by all parties to the test.
test method are defined in 5.4.
For oxides thicker than about 20 nm, the oxide electric field has
3.1.2 soft failure—failure of an MOS capacitor sensed by its
been commonly estimated by dividing the applied voltage by
passage of an electrical current equal to or greater than a
the oxide thickness, but for thinner films, significant errors may
predetermined value.
be introduced by ignoring the effects of non-zero flat band
3.1.2.1 Discussion—This type of failure may be either
voltage of the MOS capacitor and voltages developed across
destructive or nondestructive, as in the case of Fowler-
the silicon substrate (and the gate electrode as well, if it is
Nordheim or direct tunneling currents.
polysilicon) due to band bending and series resistance. One
3.1.3 failure modes A, B, and C—in the reporting of hard
approach to estimation of the relationship between sample
and soft breakdown failure results, data is sometimes summa-
parameters and oxide field strength is found in 10.2.
rized in terms of ranges of oxide field strength in which the
4.3 Current Sampling—In order to provide adequate break-
3,4
breakdown occurred. One set of categories widely used is as
down field strength resolution, it is specified that current
follows:
readings be taken after a maximum electric field change of 0.1
A mode failure: V => E < 1 MV/cm
bd ox
MV/cm. Taken together with the specified voltage ramp rate,
B mode failure: V => E < 1 MV/cm, <=8 mV/cm
bd ox
this leads to a maximum time between current readings of 100
C mode failure: V => E < 8 MV/cm.
bd ox
ms. In the case in which the test is done using a voltage
3.1.3.1 Discussion—These categories have traditionally
staircase, this implies use of a 100-ms voltage step duration,
been used for oxides thicker than about 20 nm. For thinner
with one current reading taken at each step.
films, care must be taken in their use and in proper derivation
4.4 Failure Criteria—As previously mentioned, both
of the oxide field strengths as described in 10.2.
“hard” and “soft” failure criteria are provided for in this test
methods (see Section 3 on Terminology). Techniques for
detection of hard oxide failure for thin dielectrics may require
Yamabe, K., Ozawa, Y., Nadahara, S., and Imai, K., “Thermally Grown Silicon
Dioxide with High Reliability,” in”Semiconductor Silicon 1990”, Proceedings of the
high resolution, low noise current-voltage data. For this reason,
1990 Spring Meeting of The Electrochemical Society, p. 349.
hard failure criteria are defined in two measurement regimes,
Yamabe, K., Taniguchi, K., and Matsushita, Y., “Thickness Dependence of
one below and one above a threshold current level where noise
Dielectric Breakdown Failure of Thermal SiO Films,” Reliability Physics—21st
Annual Proceedings, 1983, p. 184. is reduced. This current level is commonly in the range 1 nA to
NOTICE: This standard has either been superceded and replaced by a new version or discontinued.
Contact ASTM International (www.astm.org) for the latest information.
F 1771 – 97 (2002)
0.1 μA for most test systems. Hard failure criteria below the integrity data via the voltage ramp technique among interested
noise threshold level are defined as follows: parties. However, since the values obtained cannot be entirely
4.4.1 Current greater than or equal to 0.98 times the divorced from the process of fabricating the test structure,
compliance limit of the current score: This condition signals suitable correlations should be performed based on process
total collapse of the capacitor. needs and structure selection. This correlation should include
4.4.2 Current change by a factor of 1000 in a single voltage sample size as well as device geometry.
step: Units with gross defects failing at low voltages where 5.2 Measurement of the electrical integrity of oxides grown
currents are below the noise threshold commonly fail with very on silicon wafers may also be used in-house as a means of
large increases in current. monitoring the quality of furnaces and other processing steps
4.4.3 Consecutive current increases by a factor of 10 in as well as judging the impact of changing some processing
each of two voltage steps: Test capacitors that are initially steps.
highly conductive, as from a pinhole, often do not display 5.3 Selection of various edge and area intensive structures is
destructive breakdown, but rather show steeply rising diodic crucial for isolating the nature of the defects. Techniques for
leakage currents. This failure criterion is designed to identify using such structures to isolate the nature of detected defects is
these defective units at low voltage. Above the noise threshold beyond the scope of this test method.
current level, the two criteria above remain in force, and two 5.4 The actual results will be somewhat dependent on the
others are added, as follows: choice of gate electrode. Polysilicon gates have the advantage
4.4.4 Current change by a factor of 10 in a single step: In of being identical to finished product in many instances. Even
the Fowler-Nordheim regime, current changes are much less for polysilicon gates, exact results will depend upon values
than this value for the small increment in oxide field associated chosen for polysilicon thickness, doping, and sheet resistance.
with a single voltage step.
6. Interferences
4.4.5 Change in the logarithmic slope of the J-V curve by a
6.1 Since this is a dc measurement, care
...