Standard Practice for Detection of Oxidation Induced Defects in Polished Silicon Wafers (Withdrawn 2003)

SCOPE
This standard was transferred to SEMI (www.semi.org) May 2003
1.1 This practice covers the detection of crystalline defects in the surface region of silicon wafers. The defects are induced or enhanced by oxidation cycles encountered in normal device processing. An atmospheric pressure, oxidation cycle representative of bipolar, metal-oxide-silicon (MOS) and CMOS technologies is included. This practice is required to reveal strain fields arising from the presence of precipitates, oxidation induced stacking faults, and shallow etch pits. Slip is also revealed that arises when internal or edge stresses are applied to the wafer.
1.2 Application of this practice is limited to specimens that have been chemical or chemical/mechanical polished to remove surface damage from at lease one side of the specimen. This practice may also be applied to detection of defects in epitaxial layers.
1.3 The surface of the specimen opposite the surface to be investigated may be damaged deliberately or otherwise treated for gettering purposes or chemically etched to remove damage.
1.4 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

General Information

Status
Withdrawn
Publication Date
09-Dec-2002
Withdrawal Date
09-May-2003
Technical Committee
Current Stage
Ref Project

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ASTM F1727-02 - Standard Practice for Detection of Oxidation Induced Defects in Polished Silicon Wafers (Withdrawn 2003)
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NOTICE: This standard has either been superceded and replaced by a new version or discontinued.
Contact ASTM International (www.astm.org) for the latest information.
Designation: F 1727 – 02
Standard Practice for
Detection of Oxidation Induced Defects in Polished Silicon
1
Wafers
This standard is issued under the fixed designation F 1727; the number immediately following the designation indicates the year of
original adoption or, in the case of revision, the year of last revision. A number in parentheses indicates the year of last reapproval. A
superscript epsilon (e) indicates an editorial change since the last revision or reapproval.
1. Scope F 1809 Guide for Selection and Use of Etching Solutions to
3
Delineate Structural Defects in Silicon
1.1 This practice covers the detection of crystalline defects
F 1810 Test Method for Counting Preferentially Etched or
in the surface region of silicon wafers. The defects are induced
3
Decorated Surface Defects in Silicon Wafers
or enhanced by oxidation cycles encountered in normal device
4
2.2 SEMI Specifications:
processing. An atmospheric pressure, oxidation cycle represen-
C3.19 Standard for Hydrogen (H ) 99.9995 % Quality
tative of bipolar, metal-oxide-silicon (MOS) and CMOS tech- 2
C3.23 Standard for Oxygen (O ) 99.98 % Quality
2
nologies is included. This practice is required to reveal strain
C28 Specifications and Guidelines for Hydrofluoric Acid
fields arising from the presence of precipitates, oxidation
induced stacking faults, and shallow etch pits. Slip is also
3. Terminology
revealed that arises when internal or edge stresses are applied
3.1 Defect-related terminology may be found in Terminol-
to the wafer.
ogy F 1241.
1.2 Application of this practice is limited to specimens that
have been chemical or chemical/mechanical polished to re-
4. Summary of Practice
move surface damage from at least one side of the specimen.
4.1 Wet oxidation is used to generate or highlight defects, or
This practice may also be applied to detection of defects in
both, in silicon wafers. This oxidation may also simulate
epitaxial layers.
simple device production processes. The defects are revealed
1.3 The surface of the specimen opposite the surface to be
subsequently by preferential etching and examination by inter-
investigated may be damaged deliberately or otherwise treated
ference contrast microscopy according to referenced ASTM
for gettering purposes or chemically etched to remove damage.
standards.
1.4 This standard does not purport to address all of the
safety concerns, if any, associated with its use. It is the
5. Significance and Use
responsibility of the user of this standard to establish appro-
5.1 Defects induced by thermal processing of silicon wafers
priate safety and health practices and determine the applica-
may adversely influence device performance and yield.
bility of regulatory limitations prior to use.
5.2 These defects are influenced directly by contamination,
ambient atmosphere, temperature, time at temperature, and rate
2. Referenced Documents
of change of temperature to which the specimens are subjected.
2.1 ASTM Standards:
Conditions vary significantly among device manufacturing
D 5127 Guide for Ultra Pure Water Used in the Electronics
2 technologies. The thermal cycling procedures of this practice
and Semiconductor Industry
are intended to simulate basic device processing technologies.
3
F 1241 Terminology of Silicon Technology
Oxidation cycles other than specified herein, or multiple
F 1725 Guide for Analysis of Crystallographic Perfection of
oxidation cycles, may sometimes more accurately simulate
3
Silicon Ingots
device processing procedures. The results obtained may differ
F 1726 Guide for Analysis of Crystallographic Perfection of
significantly from those obtained with the specified oxidation
3
Silicon Wafers
cycles.
5.3 The geometry of some patterns revealed by this practice
suggests that they are related to the crystal growth process
1
This practice is under the jurisdiction of ASTM Committee F01 on Electronics
while others seem related to surface preparation or thermal
and is the direct responsibility of Subcommittee F01.06 on Silicon Materials and
cycling conditions.
Process Control.
Current edition approved Dec. 10, 2002. Published February 2003. Originally
approved 1997. Last previous edition approved in 1997 as F 1727–97.
2 4
Annual Book of ASTM Standards, Vol 11.01. Available from Semiconductor Equipment and Materials International, 3081
3
Annual Book of ASTM Standards, Vol 10.05. Zanker Road, San Jose, CA 95134 (www.semi.org).
Copyright © ASTM International, 100 Barr Harbor Drive, PO Box C700, West Conshohocken, PA 19428-2959, United States.
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NOTICE: This standard has either been superceded and replaced by a new version or discontinued.
Contact ASTM International (www.astm.org) for the latest information.
F1727–02
5.4 This practice is suitable for acceptance testing when where they e
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