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ASTM F1727-97

(Practice)

Standard Practice for Detection of Oxidation Induced Defects in Polished Silicon Wafers

Standard Practice for Detection of Oxidation Induced Defects in Polished Silicon Wafers

SCOPE
1.1 This practice covers the detection of crystalline defects in the surface region of silicon wafers. The defects are induced or enhanced by oxidation cycles encountered in normal device processing. An atmospheric pressure, oxidation cycle representative of bipolar, metal-oxide-silicon (MOS) and CMOS technologies is included. This practice is required to reveal strain fields arising from the presence of precipitates, oxidation induced stacking faults, and shallow etch pits. Slip is also revealed that arises when internal or edge stresses are applied to the wafer.
1.2 Application of this practice is limited to specimens that have been chemical or chemical/mechanical polished to remove surface damage from at lease one side of the specimen. This practice may also be applied to detection of defects in epitaxial layers.
1.3 The surface of the specimen opposite the surface to be investigated may be damaged deliberately or otherwise treated for gettering purposes or chemically etched to remove damage.
1.4 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

General Information

Status
Historical
Publication Date
09-Jun-1997
ICS
29.045 - Semiconducting materials
Technical Committee
F01 - Electronics
Current Stage
Ref Project

Relations

Replaced By
ASTM F1727-02 - Standard Practice for Detection of Oxidation Induced Defects in Polished Silicon Wafers (Withdrawn 2003)
Effective Date
10-Dec-2002

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ASTM F1727-97 - Standard Practice for Detection of Oxidation Induced Defects in Polished Silicon WafersASTM F1727-97 - Standard Practice for Detection of Oxidation Induced Defects in Polished Silicon Wafers
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ASTM F1727-97 - Standard Practice for Detection of Oxidation Induced Defects in Polished Silicon Wafers
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NOTICE: This standard has either been superseded and replaced by a new version or withdrawn. Contact
ASTM International (www.astm.org) for the latest information.
Designation: F 1727 – 97
AMERICAN SOCIETY FOR TESTING AND MATERIALS
100 Barr Harbor Dr., West Conshohocken, PA 19428
Reprinted from the Annual Book of ASTM Standards. Copyright ASTM
Standard Practice for
Detection of Oxidation Induced Defects in Polished Silicon
1
Wafers
This standard is issued under the fixed designation F 1727; the number immediately following the designation indicates the year of
original adoption or, in the case of revision, the year of last revision. A number in parentheses indicates the year of last reapproval. A
superscript epsilon (e) indicates an editorial change since the last revision or reapproval.
4
1. Scope 2.2 SEMI Specifications:
SEMI C-1 Specification for Reagents
1.1 This practice covers the detection of crystalline defects
SEMI C-3 Specifications for Gases
in the surface region of silicon wafers. The defects are induced
or enhanced by oxidation cycles encountered in normal device
3. Terminology
processing. An atmospheric pressure, oxidation cycle represen-
3.1 Defect-related terminology may be found in Terminol-
tative of bipolar, metal-oxide-silicon (MOS) and CMOS tech-
ogy F 1241.
nologies is included. This practice is required to reveal strain
fields arising from the presence of precipitates, oxidation
4. Summary of Practice
induced stacking faults, and shallow etch pits. Slip is also
4.1 Wet oxidation is used to generate or highlight defects, or
revealed that arises when internal or edge stresses are applied
both, in silicon wafers. This oxidation may also simulate
to the wafer.
simple device production processes. The defects are revealed
1.2 Application of this practice is limited to specimens that
subsequently by preferential etching and examination by inter-
have been chemical or chemical/mechanical polished to re-
ference contrast microscopy according to referenced ASTM
move surface damage from at least one side of the specimen.
standards.
This practice may also be applied to detection of defects in
epitaxial layers.
5. Significance and Use
1.3 The surface of the specimen opposite the surface to be
5.1 Defects induced by thermal processing of silicon wafers
investigated may be damaged deliberately or otherwise treated
may adversely influence device performance and yield.
for gettering purposes or chemically etched to remove damage.
5.2 These defects are influenced directly by contamination,
1.4 This standard does not purport to address all of the
ambient atmosphere, temperature, time at temperature, and rate
safety concerns, if any, associated with its use. It is the
of change of temperature to which the specimens are subjected.
responsibility of the user of this standard to establish appro-
Conditions vary significantly among device manufacturing
priate safety and health practices and determine the applica-
technologies. The thermal cycling procedures of this practice
bility of regulatory limitations prior to use.
are intended to simulate basic device processing technologies.
Oxidation cycles other than specified herein, or multiple
2. Referenced Documents
oxidation cycles, may sometimes more accurately simulate
2.1 ASTM Standards:
device processing procedures. The results obtained may differ
2
D 5127 Guide for Electronic Grade Water
significantly from those obtained with the specified oxidation
3
F 1241 Terminology of Silicon Technology
cycles.
F 1725 Guide for Analysis of Crystallographic Perfection of
5.3 The geometry of some patterns revealed by this practice
3
Silicon Ingots
suggests that they are related to the crystal growth process
F 1726 Guide for Analysis of Crystallographic Perfection of
while others seem related to surface preparation or thermal
3
Silicon Wafers
cycling conditions.
F 1809 Guide for Selection and Use of Etching Solutions to
5.4 This practice is suitable for acceptance testing when
3
Delineate Structural Defects in Silicon
used with referenced practices and methods.
F 1810 Test Method for Counting Preferentially Etched or
3
6. Interferences
Decorated Surface Defects in Silicon Wafers
6.1 Material having residual work damage in the polished
surface exhibits visible patterns when the procedures of this
1
This practice is under the jurisdiction of ASTM Committee F-1 on Electronics
practice are used. Usually, edge damage, lapping damage, tool
and is the direct responsibility of Subcommittee F01.06 on Silicon Materials and
Process Control.
Current edition approved June 10, 1997. Published August, 1997.
2 4
Annual Book of ASTM Standards, Vol 11.01. Available from Semiconductor Equipment and Materials International, 805 E
3
Annual Book of ASTM Standards, Vol 10.05. Middlefield Rd., Mountain View, CA 94043.
1

---------------------- Page: 1 ----------------------
NOTICE:¬This¬standard¬has¬either¬been¬superceded¬and¬replaced¬by¬a¬new¬version¬or¬discontinued.¬
Contact¬ASTM¬International¬(www.as
...

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