Space engineering - ASIC, FPGA and IP Core engineering

This standard specifies a comprehensive set of engineering requirements for the
successful development of digital, analogue and mixed analogue-digital signal
custom designed integrated circuits, such as application specific integrated
circuits (ASICs), field programmable gate arrays (FPGAs) and Intellectual
Property Cores (IP Cores), from now on referred to with the single and generic
term DEVICEs.
Microelectronics systems created by more than one DEVICE die but that are
interconnected and packaged together as a single DEVICE are not considered
single monolithic DEVICEs. However ECSS-ST-20-40 is to be applied to (a) the
development of each individual monolithic die, (b) also for their integration onto
a multi-die single DEVICE considering those dice as IP Cores.
This standard may be tailored for the specific characteristic and constraints of a
space project in conformance with ECSS-S-ST-00. A pre-tailoring based on the
actual DEVICE type and criticality category of the DEVICE is addressed in
clause 5.1.2.
This standard does not cover requirements for the selection, control, procurement
or usage of DEVICEs for space projects nor DEVICE ESCC qualification
requirements, as those requirements are covered by ECSS-Q-ST-60C EEE
components standard and the ESCC generic specification No. 9000 respectively.
Nevertheless, this standard contemplates the possibility for the DEVICE to
undergo ESCC qualification after the DEVICE customer acceptance as an ECSS
qualified DEVICE, and thus a DEVICE ESCC Detail Specification and DEVICE
Radiation Test Plan and Report are optional expected outputs.

Raumfahrttechnik - ASIC und FPGA Technik

Ingénierie spatiale - Ingénierie des ASIC, FPGA et noyaux de PI

Vesoljska tehnika - Inženiring ASIC, FPGA in jedra IP

Ta standard določa izčrpen sklop zahtev za inženiring za uspešen razvoj digitalnih, analognih in mešanih analogno-digitalnih prilagojeno oblikovanih integriranih vezij, kot so aplikacijsko specifična vezja (ASIC), terensko programirljiva logična vezja (FPGA) in jedra intelektualne lastnine (jedra IP), v nadaljevanju poimenovani z enim in splošnim
izrazom NAPRAVA.
Mikroelektronski sistemi, ki jih sestavlja več kot en čip NAPRAVE, vendar so med seboj povezani in združeni kot ena NAPRAVA, se ne štejejo kot ena monolitna NAPRAVA. Vendar pa se standard ECSS-ST-20-40 uporablja za (a) razvoj vsakega posameznega monolitnega čipa, (b) tudi za njihovo integracijo v eno NAPRAVO z več čipi, pri čemer so ti čipi jedra intelektualne lastnine.
Ta standard se lahko prilagodi posameznim lastnostim in omejitvam vesoljskega projekta v skladu s standardom ECSS-S-ST-00. Predhodno prilagajanje na podlagi dejanske vrste NAPRAVE in kritične kategorije NAPRAVE je obravnavno v točki 5.1.2.
Ta standard ne zajema zahtev za izbiro, nadzor, nabavo in uporabo NAPRAV za vesoljske projekte ali zahtev za kvalifikacijo po standardu ESCC za NAPRAVE, saj so te zahteve zajete v standardu o električnih, elektronskih in elektromehanskih komponentah ECSS-Q-ST-60C oziroma splošni specifikaciji št. 9000 sistema ESCC.
Vseeno pa ta standard obravnava možnost, da se za NAPRAVO izvede kvalifikacija po sistemu ECSS potem, ko je stranka NAPRAVO sprejela kot NAPRAVO s kvalifikacijo po sistemu ECSS, s tem pa so podrobna specifikacija NAPRAVE po sistemu ESCC in načrt in poročilo o preskusu sevanja NAPRAVE izbirni pričakovani rezultati.

General Information

Public Enquiry End Date
Publication Date
Technical Committee
Current Stage
6060 - National Implementation/Publication (Adopted Project)
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Standards Content (Sample)

SIST EN 16603-20-40:2024
Vesoljska tehnika - Inženiring ASIC, FPGA in jedra IP
Space engineering - ASIC, FPGA and IP Core engineering
Raumfahrttechnik - ASIC und FPGA Technik
Ingénierie spatiale - Ingénierie des ASIC, FPGA et noyaux de PI
Ta slovenski standard je istoveten z: EN 16603-20-40:2023
49.140 Vesoljski sistemi in operacije Space systems and
SIST EN 16603-20-40:2024 en,fr,de
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

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SIST EN 16603-20-40:2024

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SIST EN 16603-20-40:2024



December 2023
ICS 49.140

English version

Space engineering - ASIC, FPGA and IP Core engineering
Ingénierie spatiale - Ingénierie des ASIC, FPGA et Raumfahrttechnik - Entwicklung von ASICs, FPGAs und
noyaux de PI IP-Kernen
This European Standard was approved by CEN on 3 December 2023.

CEN and CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for
giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical
references concerning such national standards may be obtained on application to the CEN-CENELEC Management Centre or to
any CEN and CENELEC member.

This European Standard exists in three official versions (English, French, German). A version in any other language made by
translation under the responsibility of a CEN and CENELEC member into its own language and notified to the CEN-CENELEC
Management Centre has the same status as the official versions.

CEN and CENELEC members are the national standards bodies and national electrotechnical committees of Austria, Belgium,
Bulgaria, Croatia, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy,
Latvia, Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Republic of North Macedonia, Romania, Serbia,
Slovakia, Slovenia, Spain, Sweden, Switzerland, Türkiye and United Kingdom.

CEN-CENELEC Management Centre:
Rue de la Science 23, B-1040 Brussels
© 2023 CEN/CENELEC All rights of exploitation in any form and by any means
Ref. No. EN 16603-20-40:2023 E
reserved worldwide for CEN national Members and for
CENELEC Members.

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SIST EN 16603-20-40:2024
EN 16603-20-40:2023 (E)
Table of contents
European Foreword .6
Introduction .7
1 Scope .8
2 Normative references .9
3 Terms, definitions and abbreviated terms . 10
3.1 Terms from other standards .10
3.2 Terms specific to the present standard .10
3.3 Abbreviated terms .17
3.4 Conventions .19
3.4.1 Names of DEVICE development phases and reviews . 19
3.4.2 Companies involved in the DEVICE development . 20
3.4.3 Types of DEVICEs and requirements tailoring tag notation . 20
3.5 Nomenclature .21
4 Principles . 22
4.1 DEVICE development .22
4.2 Verification methods .22
5 DEVICE engineering . 23
5.1 General requirements .23
5.1.1 Overview .23
5.1.2 Tailoring according to DEVICE type and DEVICE criticality .

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