EN 61523-1:2002

Delay and power calculation standards - Part 1: Integrated circuit delay and power calculation systems

The scope of the DPCS standard is to make it possible for integrated circuit designers to analyze chip timing and power consistently across a broad set of EDA applications, for integrated circuit vendors to express timing and power information once (for a given technology), and for EDA vendors to meet their application performance and capacity needs.

Berechnung von Verzögerung und Leistungsaufnahme beim Entwurf von Chips - Teil 1: System zur Berechnung von Verzögerung und Leistungsaufnahme integrierter Schaltkreise (IC)

Normes de calculs de puissance et de temps de retard - Partie 1: Systèmes de calcul de puissance et de temps de retard des circuits intégrés

seulement disponible en anglais

Delay and power calculation standards - Part 1: Integrated circuit delay and power calculation systems (IEC 61523-1:2001)

General Information

• Status: Withdrawn
• Publication Date: 10-Jan-2002
• Withdrawal Date: 30-Nov-2004
• ICS: 35.240.50 - IT applications in industry
• Technical Committee: CLC/SR 91 - Electronics assembly technology
• Drafting Committee: IEC/TC 93 - IEC_TC_93
• Parallel Committee: IEC/TC 93 - IEC_TC_93
• Ref Project: SIST EN 61523-1:2002 - Delay and power calculation standards -- Part 1: Integrated circuit delay and power calculation systems

Standards Content (Sample)

SLOVENSKI STANDARD
SIST EN 61523-1:2002
01-september-2002
Delay and power calculation standards - Part 1: Integrated circuit delay and power
calculation systems (IEC 61523-1:2001)
Delay and power calculation standards -- Part 1: Integrated circuit delay and power
calculation systems
Berechnung von Verzögerung und Leistungsaufnahme beim Entwurf von Chips -- Teil 1:
System zur Berechnung von Verzögerung und Leistungsaufnahme integrierter
Schaltkreise (IC)
Normes de calculs de puissance et de temps de retard -- Partie 1: Systèmes de calcul de
puissance et de temps de retard des circuits intégrés
Ta slovenski standard je istoveten z: EN 61523-1:2002
ICS:
31.200 Integrirana vezja, Integrated circuits.
mikroelektronika Microelectronics
SIST EN 61523-1:2002 en
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

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SIST EN 61523-1:2002

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SIST EN 61523-1:2002
EUROPEAN STANDARD EN 61523-1
NORME EUROPÉENNE
EUROPÄISCHE NORM January 2002
ICS 35.240.50
English version
Delay and power calculation standards
Part 1: Integrated circuit delay and power
calculation systems
(IEC 61523-1:2001)
Normes de calculs de puissance Berechnung von Verzögerung
et de temps de retard und Leistungsaufnahme beim
Partie 1: Systèmes de calcul Entwurf von Chips
de puissance et de temps Teil 1: System zur Berechnung von
de retard des circuits intégrés Verzögerung und Leistungsaufnahme
(CEI 61523-1:2001) integrierter Schaltkreise (IC)
(IEC 61523-1:2001)
This European Standard was approved by CENELEC on 2001-12-04. CENELEC members are bound to
comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European
Standard the status of a national standard without any alteration.
Up-to-date lists and bibliographical references concerning such national standards may be obtained on
application to the Central Secretariat or to any CENELEC member.
This European Standard exists in three official versions (English, French, German). A version in any other
language made by translation under the responsibility of a CENELEC member into its own language and
notified to the Central Secretariat has the same status as the official versions.
CENELEC members are the national electrotechnical committees of Austria, Belgium, Czech Republic,
Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Malta, Netherlands,
Norway, Portugal, Spain, Sweden, Switzerland and United Kingdom.
CENELEC
European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung
Central Secretariat: rue de Stassart 35, B - 1050 Brussels
© 2002 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members.
Ref. No. EN 61523-1:2002 E

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SIST EN 61523-1:2002
EN 61523-1:2002 - 2 -
Foreword
The text of document 93/143/FDIS, future edition 1 of IEC 61523-1, prepared by IEC TC 93, Design
automation, was submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as
EN 61523-1 on 2001-12-04.
The following dates were fixed:
– latest date by which the EN has to be implemented
at national level by publication of an identical
national standard or by endorsement (dop) 2002-09-01
– latest date by which the national standards conflicting
with the EN have to be withdrawn (dow) 2004-12-01
This standard is based on IEEE Std P1481:1999; IEEE Standard for delay and power calculation
systems.
__________
Endorsement notice
The text of the International Standard IEC 61523-1:2001 was approved by CENELEC as a European
Standard without any modification.
__________

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SIST EN 61523-1:2002
INTERNATIONAL IEC
STANDARD
61523-1
First edition
2001-09
Delay and power calculation standards –
Part 1:
Integrated circuit delay and power calculation
systems
 IEC 2001  Copyright - all rights reserved
No part of this publication may be reproduced or utilized in any form or by any means, electronic or
mechanical, including photocopying and microfilm, without permission in writing from the publisher.
International Electrotechnical Commission 3, rue de Varembé Geneva, Switzerland
Telefax: [phone] e-mail: [e-mail] IEC web site http://www.iec.ch
Commission Electrotechnique Internationale
PRICE CODE
XP
International Electrotechnical Commission
For price, see current catalogue

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SIST EN 61523-1:2002
– 2 – 61523-1  IEC:2001(E)
Contents
SECTION PAGE
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
...