IEC 62878-2-5:2019

Device embedding assembly technology - Part 2-5: Guidelines - Implementation of a 3D data format for device embedded substrate

IEC 62878-2-5:2019 specifies requirements based on XML schema that represents a design data format for device embedded substrate, which is a board comprising embedded active and passive devices whose electrical connections are made by means of a via, electroplating, conductive paste or printing of conductive material.
This data format is to be used for simulation (e.g. stress, thermal, EMC), tooling, manufacturing, assembly, and inspection requirements. Furthermore, the data format is used for transferring information among printed board designers, printed board simulation engineer, manufacturers, and assemblers.
IEC 62878-2-5:2019 applies to substrates using organic material. It neither applies to the re-distribution layer (RDL) nor to the electronic modules defined as M-type business model in IEC 62421.

Technologie d’ensemble avec appareil(s) intégré(s) - Partie 2-5 : Lignes directrices - Mise en œuvre d’un format de données 3D pour un substrat avec appareil(s) intégré(s)

L’IEC 62878-2-5:2019 spécifie des exigences fondées sur le schéma XML qui représente un format de données de conception pour le substrat avec appareil(s) intégré(s), c’est-à-dire une carte avec appareil(s) intégré(s) actif(s) ou passif(s) dont les connexions électriques se font au moyen d’un trou de liaison, de galvanoplastie, de pâte conductrice ou d’impression du matériau conducteur.
Ce format de données doit être utilisé pour les exigences de simulation (par exemple, contrainte, thermique, compatibilité électromagnétique), d’outillage, de fabrication, d’assemblage et d’examen. De plus, le format de données est utilisé pour le transfert d’informations entre les concepteurs de cartes imprimées, les ingénieurs de simulation des cartes imprimées, les fabricants et les assembleurs.
La présente partie de l’IEC 62878 s’applique aux substrats utilisant des matériaux organiques. Elle ne s'applique ni à la couche de redistribution (RDL, re-distribution layer), ni aux modules électroniques définis comme un modèle commercial de type M dans l'IEC 62421.

General Information

• Status: Published
• Publication Date: 15-Sep-2019
• ICS: 01 - GENERALITIES. TERMINOLOGY. STANDARDIZATION. DOCUMENTATION
• ICS: 31.180 - Printed circuits and boards
• ICS: 31.190 - Electronic component assemblies
• Technical Committee: TC 91 - Electronics assembly technology
• Drafting Committee: WG 6 - TC 91/WG 6
• Current Stage: PPUB - Publication issued
• Start Date: 14-Oct-2019
• Completion Date: 16-Sep-2019

Relations

• Revises: IEC PAS 62878-2-5:2015 - Device embedded substrate - Guidelines - Data format
• Effective Date: 05-Sep-2023

Standards Content (Sample)

IEC 62878-2-5 ®
Edition 1.0 2019-09
INTERNATIONAL
STANDARD
colour
inside
Device embedding assembly technology –
Part 2-5: Guidelines – Implementation of a 3D data format for device embedded
substrate
All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form
or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from
either IEC or IEC's member National Committee in the country of the requester. If you have any questions about IEC
copyright or have an enquiry about obtaining additional rights to this publication, please contact the address below or
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About the IEC
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International Standards for all electrical, electronic and related technologies.

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IEC 62878-2-5 ®
Edition 1.0 2019-09
INTERNATIONAL
STANDARD
colour
inside
Device embedding assembly technology –

Part 2-5: Guidelines – Implementation of a 3D data format for device embedded

substrate
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 31.180; 31.190 ISBN 978-2-8322-7399-9

– 2 – IEC 62878-2-5:2019 © IEC 2019
CONTENTS
FOREWORD . 5
1 Scope . 7
2 Normative references . 7
3 Terms and definitions . 7
4 Data definition . 10
4.1 Flow chart design of device embedded substrate . 10
4.2 Applicable range . 11
4.2.1 Product . 11
4.2.2 Process . 12
4.3 Features . 13
4.3.1 General . 13
4.3.2 Device embedded substrate structure . 13
4.3.3 SiP interposer structure . 14
4.3.4 Virtual layer description . 15
4.3.5 Terminal structure and embedded device structure including an SiP . 15
4.3.6 Total design data of an SiP and device embedded substrate . 15
4.4 Data description summary . 16
4.4.1 Type of data and structures . 16
4.4.2 File structure . 18
4.5 3D expression . 19
4.5.1 General . 19
4.5.2 Coordinates . 19
4.5.3 Position description . 20
4.5.4 Relation between coordinate origin and board position . 20
4.6 Layer concept . 21
4.7 Substrate data . 21
4.7.1 General . 21
4.7.2 Layer map information . 22
4.7.3 Device arrangement information . 23
4.7.4 Basic figures . 25
4.7.5 Net information . 31
4.7.6 Artwork information . 32
4.7.7 Package information . 32
4.7.8 External port information. 33
4.7.9 Internal port information . 33
4.7.10 User expansion information . 33
4.8 Defined data . 33
4.8.1 General . 33
4.8.2 Layer definition . 33
4.8.3 Land definition . 34
4.8.4 Via definition . 35
4.8.5 Device definition . 36
4.8.6 User expansion definition . 37
5 Data organization and data description based on XML schema . 38
5.1 General . 38
5.2 Data organization of Example 1 . 38
5.3 Data description of layer stack-up . 39

5.4 Data description of device . 43
5.5 Data organization of layer . 47
5.6 Data description of via . 50
5.7 Data description of land . 51
Bibliography . 53

Figure 1 – Flow chart of design of device embedded substrate . 11
Figure 2 – General structure of device embedded substrate . 12
Figure 3 – Example of device embedded substrate structure. 14
Figure 4 – Examples of SiPs . 14
Figure 5 – Example of virtual layer description . 15
Figure 6 – Terminal structure . 15
Figure 7 – Structure of SiP on a device embedded substrate . 16
Figure 8 – Data structure . 18
Figure 9 – One file structure (recommended) . 19
Figure 10 – Two file structure . 19
Figure 11 – Definition of coordinates . 20
Figure 12 – Position definition . 20
Figure 13 – Relation between coordinates and board position . 21
Figure 14 – Layer concept . 21
Figure 15 – Layer construction . 22
Figure 16 – Simplified layer construction . 23
Figure 17 – Layer definition of pad connection . 24
Figure 18 – Layer definition of via connection . 24
Figure 19 – Rotation direction on X, Y, and Z axes . 25
Figure 20 – Point . 26
Figure 21 – Area . 27
Figure 22 – Lines . 27
Figure 23 – Letters . 28
Figure 24 – Letter shape . 28
Figure 25 – Bonding wire information . 29
Figure 26 – Semi-sphere . 29
Figure 27 – Truncated pyramid . 30
Figure 28 – Via . 30
Figure 29 – Device definition . 31
Figure 30 – Group . 31
Figure 31 – Data structure of net information . 32
Figure 32 – Relation of layer definition data . 34
Figure 33 – Land definition . 35
Figure 34 – Relation between hole information and land information . 36
Figure 35 – Device with internal connection information . 37
Figure 36 – Device without internal connection information . 37
Figure 37 – Cross sectional view of Example 1 . 38
Figure 38 – Data organization of Example 1 . 38

– 4 – IEC 62878-2-5:2019 © IEC 2019
Figure 39 – Data descripion of Example 1 . 39
Figure 40 – Layer structure of Example 1 . 40
Figure 41 – Data description of lay
...

IEC 62878-2-5 ®
Edition 1.0 2019-09
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Device embedding assembly technology –
Part 2-5: Guidelines – Implementation of a 3D data format for device embedded
substrate
Technologie d’ensemble avec appareil(s) intégré(s) –
Partie 2-5: Lignes directrices – Mise en œuvre d’un format de données 3D
pour un substrat avec appareil(s) intégré(s)

All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form
or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from
either IEC or IEC's member National Committee in the country of the requester. If you have any questions about IEC
copyright or have an enquiry about obtaining additional rights to this publication, please contact the address below or
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About the IEC
The International Electrotechnical Commission (IEC) is the leading global organization that prepares and publishes
International Standards for all electrical, electronic and related technologies.

About IEC publications
The technical content of IEC publications is kept under constant review by the IEC. Please make sure that you have the
latest edition, a corrigendum or an amendment might have been published.

IEC publications search - webstore.iec.ch/advsearchform Electropedia - www.electropedia.org
The advanced search enables to find IEC publications by a The world's leading online dictionary on electrotechnology,
variety of criteria (reference number, text, technical containing more than 22 000 terminological entries in English
committee,…). It also gives information on projects, replaced and French, with equivalent terms in 16 additional languages.
and withdrawn publications. Also known as the International Electrotechnical Vocabulary

(IEV) online.
IEC Just Published - webstore.iec.ch/justpublished
Stay up to date on all new IEC publications. Just Published IEC Glossary - std.iec.ch/glossary
details all new publications released. Available online and 67 000 electrotechnical terminology entries in English and
once a month by email. French extracted from the Terms and Definitions clause of
IEC publications issued since 2002. Some entries have been
IEC Customer Service Centre - webstore.iec.ch/csc collected from earlier publications of IEC TC 37, 77, 86 and
If you wish to give us your feedback on this publication or CISPR.

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IEC 62878-2-5 ®
Edition 1.0 2019-01
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Device embedding assembly technology –

Part 2-5: Guidelines – Implementation of a 3D data format for device embedded

substrate
Technologie d’ensemble avec appareil(s) intégré(s) –

Partie 2-5: Lignes directrices – Mise en œuvre d’un format de données 3D

pour un substrat avec appareil(s) intégré(s)

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.180; 31.190 ISBN 978-2-8322-7768-3

– 2 – IEC 62878-2-5:2019 © IEC 2019
CONTENTS
FOREWORD . 5
1 Scope . 7
2 Normative references . 7
3 Terms and definitions . 7
4 Data definition . 10
4.1 Flow chart design of device embedded substrate . 10
4.2 Applicable range . 11
4.2.1 Product . 11
4.2.2 Process . 12
4.3 Features . 13
4.3.1 General . 13
4.3.2 Device embedded substrate structure . 13
4.3.3 SiP interposer structure . 14
4.3.4 Virtual layer description . 15
4.3.5 Terminal structure and embedded device structure including an SiP . 15
4.3.6 Total design data of an SiP and device embedded substrate . 15
4.4 Data description summary . 16
4.4.1 Type of data and structures . 16
4.4.2 File structure . 18
4.5 3D expression . 19
4.5.1 General . 19
4.5.2 Coordinates . 19
4.5.3 Position description . 20
4.5.4 Relation between coordinate origin and board position . 20
4.6 Layer concept . 21
4.7 Substrate data . 21
4.7.1 General . 21
4.7.2 Layer map information . 22
4.7.3 Device arrangement information . 23
4.7.4 Basic figures . 25
4.7.5 Net information . 31
4.7.6 Artwork information . 32
4.7.7 Package information . 32
4.7.8 External port information. 33
4.7.9 Internal port information . 33
4.7.10 User expansion information . 33
4.8 Defined data . 33
4.8.1 General . 33
4.8.2 Layer definition . 33
4.8.3 Land definition . 34
4.8.4 Via definition . 35
4.8.5 Device definition . 36
4.8.6 User expansion definition . 37
5 Data organization and data description based on XML schema . 38
5.1 General . 38
5.2 Data organization of Example 1 . 38
5.3 Data description of layer stack-up . 39

5.4 Data description of device . 43
5.5 Data organization of layer . 47
5.6 Data description of via . 50
5.7 Data description of land . 51
Bibliography . 53

Figure 1 – Flow chart of design of device embedded substrate . 11
Figure 2 – General structure of device embedded substrate . 12
Figure 3 – Example of device embedded substrate structure. 14
Figure 4 – Examples of SiPs . 14
Figure 5 – Example of virtual layer description . 15
Figure 6 – Terminal structure . 15
Figure 7 – Structure of SiP on a device embedded substrate . 16
Figure 8 – Data structure . 18
Figure 9 – One file structure (recommended) . 19
Figure 10 – Two file structure . 19
Figure 11 – Definition of coordinates . 20
Figure 12 – Position definition . 20
Figure 13 – Relation between coordinates and board position . 21
Figure 14 – Layer concept . 21
Figure 15 – Layer construction . 22
Figure 16 – Simplified layer construction . 23
Figure 17 – Layer definition of pad connection . 24
Figure 18 – Layer definition of via connection .
...