Device embedding assembly technology - Part 2-5: Guidelines - Implementation of a 3D data format for device embedded substrate

IEC 62878-2-5:2019 specifies requirements based on XML schema that represents a design data format for device embedded substrate, which is a board comprising embedded active and passive devices whose electrical connections are made by means of a via, electroplating, conductive paste or printing of conductive material.
This data format is to be used for simulation (e.g. stress, thermal, EMC), tooling, manufacturing, assembly, and inspection requirements. Furthermore, the data format is used for transferring information among printed board designers, printed board simulation engineer, manufacturers, and assemblers.
IEC 62878-2-5:2019 applies to substrates using organic material. It neither applies to the re-distribution layer (RDL) nor to the electronic modules defined as M-type business model in IEC 62421.

Technologie d’ensemble avec appareil(s) intégré(s) - Partie 2-5 : Lignes directrices - Mise en œuvre d’un format de données 3D pour un substrat avec appareil(s) intégré(s)

L’IEC 62878-2-5:2019 spécifie des exigences fondées sur le schéma XML qui représente un format de données de conception pour le substrat avec appareil(s) intégré(s), c’est-à-dire une carte avec appareil(s) intégré(s) actif(s) ou passif(s) dont les connexions électriques se font au moyen d’un trou de liaison, de galvanoplastie, de pâte conductrice ou d’impression du matériau conducteur.
Ce format de données doit être utilisé pour les exigences de simulation (par exemple, contrainte, thermique, compatibilité électromagnétique), d’outillage, de fabrication, d’assemblage et d’examen. De plus, le format de données est utilisé pour le transfert d’informations entre les concepteurs de cartes imprimées, les ingénieurs de simulation des cartes imprimées, les fabricants et les assembleurs.
La présente partie de l’IEC 62878 s’applique aux substrats utilisant des matériaux organiques. Elle ne s'applique ni à la couche de redistribution (RDL, re-distribution layer), ni aux modules électroniques définis comme un modèle commercial de type M dans l'IEC 62421.

General Information

Status
Published
Publication Date
15-Sep-2019
Current Stage
PPUB - Publication issued
Completion Date
16-Sep-2019
Ref Project

Buy Standard

Standard
IEC 62878-2-5:2019 - Device embedding assembly technology - Part 2-5: Guidelines - Implementation of a 3D data format for device embedded substrate
English and French language
112 pages
sale 15% off
Preview
sale 15% off
Preview

Standards Content (sample)

IEC 62878-2-5
Edition 1.0 2019-09
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Device embedding assembly technology –
Part 2-5: Guidelines – Implementation of a 3D data format for device embedded
substrate
Technologie d’ensemble avec appareil(s) intégré(s) –
Partie 2-5: Lignes directrices – Mise en œuvre d’un format de données 3D
pour un substrat avec appareil(s) intégré(s)
IEC 62878-2-5:2019-09 (en-fr)
---------------------- Page: 1 ----------------------
THIS PUBLICATION IS COPYRIGHT PROTECTED
Copyright © 2019 IEC, Geneva, Switzerland

All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form

or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from

either IEC or IEC's member National Committee in the country of the requester. If you have any questions about IEC

copyright or have an enquiry about obtaining additional rights to this publication, please contact the address below or

your local IEC member National Committee for further information.

Droits de reproduction réservés. Sauf indication contraire, aucune partie de cette publication ne peut être reproduite

ni utilisée sous quelque forme que ce soit et par aucun procédé, électronique ou mécanique, y compris la photocopie

et les microfilms, sans l'accord écrit de l'IEC ou du Comité national de l'IEC du pays du demandeur. Si vous avez des

questions sur le copyright de l'IEC ou si vous désirez obtenir des droits supplémentaires sur cette publication, utilisez

les coordonnées ci-après ou contactez le Comité national de l'IEC de votre pays de résidence.

IEC Central Office Tel.: +41 22 919 02 11
3, rue de Varembé info@iec.ch
CH-1211 Geneva 20 www.iec.ch
Switzerland
About the IEC

The International Electrotechnical Commission (IEC) is the leading global organization that prepares and publishes

International Standards for all electrical, electronic and related technologies.
About IEC publications

The technical content of IEC publications is kept under constant review by the IEC. Please make sure that you have the

latest edition, a corrigendum or an amendment might have been published.

IEC publications search - webstore.iec.ch/advsearchform Electropedia - www.electropedia.org

The advanced search enables to find IEC publications by a The world's leading online dictionary on electrotechnology,

variety of criteria (reference number, text, technical containing more than 22 000 terminological entries in English

committee,…). It also gives information on projects, replaced and French, with equivalent terms in 16 additional languages.

and withdrawn publications. Also known as the International Electrotechnical Vocabulary

(IEV) online.
IEC Just Published - webstore.iec.ch/justpublished

Stay up to date on all new IEC publications. Just Published IEC Glossary - std.iec.ch/glossary

details all new publications released. Available online and 67 000 electrotechnical terminology entries in English and

once a month by email. French extracted from the Terms and Definitions clause of

IEC publications issued since 2002. Some entries have been

IEC Customer Service Centre - webstore.iec.ch/csc collected from earlier publications of IEC TC 37, 77, 86 and

If you wish to give us your feedback on this publication or CISPR.
need further assistance, please contact the Customer Service
Centre: sales@iec.ch.
A propos de l'IEC

La Commission Electrotechnique Internationale (IEC) est la première organisation mondiale qui élabore et publie des

Normes internationales pour tout ce qui a trait à l'électricité, à l'électronique et aux technologies apparentées.

A propos des publications IEC

Le contenu technique des publications IEC est constamment revu. Veuillez vous assurer que vous possédez l’édition la

plus récente, un corrigendum ou amendement peut avoir été publié.
Recherche de publications IEC - Electropedia - www.electropedia.org

webstore.iec.ch/advsearchform Le premier dictionnaire d'électrotechnologie en ligne au

La recherche avancée permet de trouver des publications IEC monde, avec plus de 22 000 articles terminologiques en

en utilisant différents critères (numéro de référence, texte, anglais et en français, ainsi que les termes équivalents dans

comité d’études,…). Elle donne aussi des informations sur les 16 langues additionnelles. Egalement appelé Vocabulaire

projets et les publications remplacées ou retirées. Electrotechnique International (IEV) en ligne.

IEC Just Published - webstore.iec.ch/justpublished Glossaire IEC - std.iec.ch/glossary

Restez informé sur les nouvelles publications IEC. Just 67 000 entrées terminologiques électrotechniques, en anglais

Published détaille les nouvelles publications parues. et en français, extraites des articles Termes et Définitions des

Disponible en ligne et une fois par mois par email. publications IEC parues depuis 2002. Plus certaines entrées

antérieures extraites des publications des CE 37, 77, 86 et
Service Clients - webstore.iec.ch/csc CISPR de l'IEC.
Si vous désirez nous donner des commentaires sur cette
publication ou si vous avez des questions contactez-nous:
sales@iec.ch.
---------------------- Page: 2 ----------------------
IEC 62878-2-5
Edition 1.0 2019-01
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Device embedding assembly technology –
Part 2-5: Guidelines – Implementation of a 3D data format for device embedded
substrate
Technologie d’ensemble avec appareil(s) intégré(s) –
Partie 2-5: Lignes directrices – Mise en œuvre d’un format de données 3D
pour un substrat avec appareil(s) intégré(s)
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.180; 31.190 ISBN 978-2-8322-7768-3

Warning! Make sure that you obtained this publication from an authorized distributor.

Attention! Veuillez vous assurer que vous avez obtenu cette publication via un distributeur agréé.

® Registered trademark of the International Electrotechnical Commission
Marque déposée de la Commission Electrotechnique Internationale
---------------------- Page: 3 ----------------------
– 2 – IEC 62878-2-5:2019 © IEC 2019
CONTENTS

FOREWORD ........................................................................................................................... 5

1 Scope .............................................................................................................................. 7

2 Normative references ...................................................................................................... 7

3 Terms and definitions ...................................................................................................... 7

4 Data definition ............................................................................................................... 10

4.1 Flow chart design of device embedded substrate .................................................. 10

4.2 Applicable range ................................................................................................... 11

4.2.1 Product .......................................................................................................... 11

4.2.2 Process ......................................................................................................... 12

4.3 Features ............................................................................................................... 13

4.3.1 General ......................................................................................................... 13

4.3.2 Device embedded substrate structure ............................................................ 13

4.3.3 SiP interposer structure ................................................................................. 14

4.3.4 Virtual layer description ................................................................................. 15

4.3.5 Terminal structure and embedded device structure including an SiP .............. 15

4.3.6 Total design data of an SiP and device embedded substrate ......................... 15

4.4 Data description summary ..................................................................................... 16

4.4.1 Type of data and structures ........................................................................... 16

4.4.2 File structure ................................................................................................. 18

4.5 3D expression ....................................................................................................... 19

4.5.1 General ......................................................................................................... 19

4.5.2 Coordinates ................................................................................................... 19

4.5.3 Position description ....................................................................................... 20

4.5.4 Relation between coordinate origin and board position .................................. 20

4.6 Layer concept ....................................................................................................... 21

4.7 Substrate data ...................................................................................................... 21

4.7.1 General ......................................................................................................... 21

4.7.2 Layer map information ................................................................................... 22

4.7.3 Device arrangement information .................................................................... 23

4.7.4 Basic figures .................................................................................................. 25

4.7.5 Net information .............................................................................................. 31

4.7.6 Artwork information ........................................................................................ 32

4.7.7 Package information ...................................................................................... 32

4.7.8 External port information................................................................................ 33

4.7.9 Internal port information ................................................................................. 33

4.7.10 User expansion information ........................................................................... 33

4.8 Defined data ......................................................................................................... 33

4.8.1 General ......................................................................................................... 33

4.8.2 Layer definition .............................................................................................. 33

4.8.3 Land definition ............................................................................................... 34

4.8.4 Via definition ................................................................................................. 35

4.8.5 Device definition ............................................................................................ 36

4.8.6 User expansion definition .............................................................................. 37

5 Data organization and data description based on XML schema ...................................... 38

5.1 General ................................................................................................................. 38

5.2 Data organization of Example 1 ............................................................................ 38

5.3 Data description of layer stack-up ......................................................................... 39

---------------------- Page: 4 ----------------------
IEC 62878-2-5:2019 © IEC 2019 – 3 –

5.4 Data description of device ..................................................................................... 43

5.5 Data organization of layer ..................................................................................... 47

5.6 Data description of via .......................................................................................... 50

5.7 Data description of land ........................................................................................ 51

Bibliography .......................................................................................................................... 53

Figure 1 – Flow chart of design of device embedded substrate ............................................. 11

Figure 2 – General structure of device embedded substrate .................................................. 12

Figure 3 – Example of device embedded substrate structure................................................. 14

Figure 4 – Examples of SiPs ................................................................................................. 14

Figure 5 – Example of virtual layer description ...................................................................... 15

Figure 6 – Terminal structure ................................................................................................ 15

Figure 7 – Structure of SiP on a device embedded substrate ................................................ 16

Figure 8 – Data structure ...................................................................................................... 18

Figure 9 – One file structure (recommended) ........................................................................ 19

Figure 10 – Two file structure ............................................................................................... 19

Figure 11 – Definition of coordinates ..................................................................................... 20

Figure 12 – Position definition ............................................................................................... 20

Figure 13 – Relation between coordinates and board position ............................................... 21

Figure 14 – Layer concept .................................................................................................... 21

Figure 15 – Layer construction .............................................................................................. 22

Figure 16 – Simplified layer construction ............................................................................... 23

Figure 17 – Layer definition of pad connection ...................................................................... 24

Figure 18 – Layer definition of via connection ....................................................................... 24

Figure 19 – Rotation direction on X, Y, and Z axes ................................................................ 25

Figure 20 – Point .................................................................................................................. 26

Figure 21 – Area ................................................................................................................... 27

Figure 22 – Lines .................................................................................................................. 27

Figure 23 – Letters ............................................................................................................... 28

Figure 24 – Letter shape ....................................................................................................... 28

Figure 25 – Bonding wire information .................................................................................... 29

Figure 26 – Semi-sphere ....................................................................................................... 29

Figure 27 – Truncated pyramid ............................................................................................. 30

Figure 28 – Via ..................................................................................................................... 30

Figure 29 – Device definition ................................................................................................ 31

Figure 30 – Group ................................................................................................................. 31

Figure 31 – Data structure of net information ........................................................................ 32

Figure 32 – Relation of layer definition data .......................................................................... 34

Figure 33 – Land definition ................................................................................................... 35

Figure 34 – Relation between hole information and land information ..................................... 36

Figure 35 – Device with internal connection information ........................................................ 37

Figure 36 – Device without internal connection information ................................................... 37

Figure 37 – Cross sectional view of Example 1 ..................................................................... 38

Figure 38 – Data organization of Example 1 .......................................................................... 38

---------------------- Page: 5 ----------------------
– 4 – IEC 62878-2-5:2019 © IEC 2019

Figure 39 – Data descripion of Example 1 ............................................................................. 39

Figure 40 – Layer structure of Example 1 .............................................................................. 40

Figure 41 – Data description of layer stack-up ...................................................................... 42

Figure 42 – Configuration of device 1.................................................................................... 43

Figure 43 – Data description of device 1 ............................................................................... 44

Figure 44 – Configuration of device 2.................................................................................... 45

Figure 45 – Data description of device 2 ............................................................................... 46

Figure 46 – Layer view of Example 1 .................................................................................... 48

Figure 47 – Data description of layers ................................................................................... 50

Figure 48 – Type of vias ....................................................................................................... 51

Figure 49 – Data description of vias ...................................................................................... 51

Figure 50 – Type of lands ..................................................................................................... 52

Figure 51 – Data description of lands .................................................................................... 52

Table 1 – Required information ............................................................................................. 13

Table 2 – List of data ............................................................................................................ 17

---------------------- Page: 6 ----------------------
IEC 62878-2-5:2019 © IEC 2019 – 5 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
DEVICE EMBEDDING ASSEMBLY TECHNOLOGY –
Part 2-5: Guidelines – Implementation of a 3D data format
for device embedded substrate
FOREWORD

1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising

all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international

co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and in

addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports,

Publicly Available Specifications (PAS) and Guides (hereafter referred to as "IEC Publication(s)"). Their

preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with

may participate in this preparatory work. International, governmental and non-governmental organizations liaising

with the IEC also participate in this preparation. IEC collaborates closely with the International Organization for

Standardization (ISO) in accordance with conditions determined by agreement between the two organizations.

2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international

consensus of opinion on the relevant subjects since each technical committee has representation from all

interested IEC National Committees.

3) IEC Publications have the form of recommendations for international use and are accepted by IEC National

Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC

Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any

misinterpretation by any end user.

4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications

transparently to the maximum extent possible in their national and regional publications. Any divergence between

any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter.

5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity

assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any

services carried out by independent certification bodies.

6) All users should ensure that they have the latest edition of this publication.

7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and

members of its technical committees and IEC National Committees for any personal injury, property damage or

other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and expenses

arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC Publications.

8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is

indispensable for the correct application of this publication.

9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent

rights. IEC shall not be held responsible for identifying any or all such patent rights.

International Standard IEC 62878-2-5 has been prepared by IEC technical committee 91:

Electronics assembly technology.

This bilingual version (2020-01) corresponds to the monolingual English version, published in

2019-09.

This first edition cancels and replaces IEC PAS 62878-2-5 published in 2015. This edition

constitutes a technical revision.

This edition includes the following significant technical changes with respect to the previous

edition:

a) the title has been changed to "Implementation of a 3D data format for device embedded

substrate" from "Requirements of design date format for device embedded substrate";

b) the scope of this implementation has changed to not include SiPs.
---------------------- Page: 7 ----------------------
– 6 – IEC 62878-2-5:2019 © IEC 2019
The text of this International Standard is based on the following documents:
CDV Report on voting
91/1557/CDV 91/1589/RVC

Full information on the voting for the approval of this International Standard can be found in the

report on voting indicated in the above table.
The French version of this standard has not been voted upon.

This document has been drafted in accordance with the ISO/IEC Directives, Part 2.

A list of all parts in the IEC 62878 series, published under the general title Device embedding

assembly technology, can be found on the IEC website.

Future standards in this series will carry the new general title as cited above. Titles of existing

standards in this series will be updated at the time of the next edition.

The committee has decided that the contents of this document will remain unchanged until the

stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to

the specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.

IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates

that it contains colours which are considered to be useful for the correct

understanding of its contents. Users should therefore print this document using a

colour printer.
---------------------- Page: 8 ----------------------
IEC 62878-2-5:2019 © IEC 2019 – 7 –
DEVICE EMBEDDING ASSEMBLY TECHNOLOGY –
Part 2-5: Guidelines – Implementation of a 3D data format
for device embedded substrate
1 Scope

This part of IEC 62878 specifies requirements based on XML schema that represents a design

data format for device embedded substrate, which is a board comprising embedded active and

passive devices whose electrical connections are made by means of a via, electroplating,

conductive paste or printing of conductive material.

This data format is to be used for simulation (e.g. stress, thermal, EMC), tooling, manufacturing,

assembly, and inspection requirements. Furthermore, the data format is used for transferring

information among printed board designers, printed board simulation engineer, manufacturers,

and assemblers.

This part of IEC 62878 applies to substrates using organic material. It neither applies to the

re-distribution layer (RDL) nor to the electronic modules defined as M-type business model in

IEC 62421.
2 Normative references
There are no normative references in this document.
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.

ISO and IEC maintain terminological databases for use in standardization at the following

addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
3.1
artwork information

information that shows a SiP not included in net and figure data in board (symbol mark, inside

of SiP, mould, spacer, remarks, etc.)
3.2
board information
total information of a device-embedded substrate, including embedded devices
3.3
chip stack
package of semiconductor chips stacked vertically
3.4
clearance

area around a through-hole where there is no conductor to prevent electrical connection

between a large conductor area, such as that of a power supply or a ground and a plated

through-hole
---------------------- Page: 9 ----------------------
– 8 – IEC 62878-2-5:2019 © IEC 2019
3.5
computer-aided manufacturing
CAM

interactive use of computer systems, programs, and procedures in various phases of a

manufacturing process wherein the decision-making activity rests with the human operator and

a computer provides the data manipulation functions
3.6
computer-aided design
CAD

interactive use of computer systems, programs, and procedures in the design process wherein

the decision-making activity rests with the human operator and a computer provides the data

manipulation function
3.7
DXF
data format for AutoCAD

Note 1 to entry: AutoCAD is the trade name of a product supplied by Autodesk®. This information is given for the

convenience of users of this document and does not constitute an endorsement by IEC of the product named.

Equivalent products may be used if they can be shown to lead to the same results.

Note 2 to entry: It generally means a type of data format to draw figures using CAD board data.

3.8
design document
documentation of information necessary in circuit board design
3.9
device arrangement information

information that includes the position, the shape and attributes of the embedding device

included in the net information
3.10
device embedded substrate

substrate in which an active device(s) (semiconductor device) and/or passive device(s) (e.g.

resistor, capacitor) is formed using thick-film technology or by embedding it within the substrate

3.11
FLIP chip

leadless monolithic circuit element structure that electrically and mechanically interconnects to

a printed board by conductive bumps
3.12
Gerber

type of data format that consists of aperture selection and operation commands and dimensions

in X- and Y-coordinates

Note 1 to entry: The data is generally used to direct a photo-plotter in generating photo-plotted artwork.

Note 2 to entry: Gerber is the trade name of a product supplied by Ucamco. This information is given for the

convenience of users of this document and does not constitute an endorsement by IEC of the product named.

Equivalent products may be used if they can be shown to lead to the same results.

3.13
interposer

material placed between two surfaces giving electrical insulation, redistribution of electrical

connections, mechanical strength and/or controlled mechanical and thermal separation

between the two surfaces
---------------------- Page: 10 ----------------------
IEC 62878-2-5:2019 © IEC 2019 – 9 –

Note 1 to entry: An interposer may be used as a means for redistributing electrical connections and/or allowing for

different thermal expansions between adjacent surface
...

Questions, Comments and Discussion

Ask us and Technical Secretary will try to provide an answer. You can facilitate discussion about the standard in here.