oSIST prEN IEC 63419:2022
(Main)Guideline for Switching Reliability Evaluation procedures for Gallium Nitride Power Conversion Devices
Guideline for Switching Reliability Evaluation procedures for Gallium Nitride Power Conversion Devices
This publication presents guidelines for evaluating the switching reliability of GaN power switches. It is applicable to planar enhancement-mode, depletion-mode, GaN integrated power solutions and cascode GaN power switches. It covers the following aspects:
a) An approach for broad coverage, using the switching locus to represent switching stress in a standardized manner.
b) The development of a lifetime model, based upon the type of application switching locus.
c) The validation of reliable operation under application-use conditions.
The publication will result in common methods for representing, evaluating and modeling the switching stress on GaN power switches, and ensuring their reliable operation in an application.
Leitfaden für Verfahren zur Bewertung der Schaltzuverlässigkeit von Galliumnitrid-Leistungsumwandlungsgeräten
Lignes directrices relatives aux procédures d’évaluation de la fiabilité de commutation pour convertisseurs de puissance en nitrure de gallium
Smernice za postopke ocenjevanja stikalne zanesljivosti galij-nitridnih razsmernikov
General Information
Standards Content (Sample)
SLOVENSKI STANDARD
oSIST prEN IEC 63419:2022
01-april-2022
Smernice za postopke ocenjevanja stikalne zanesljivosti galij-nitridnih
razsmernikov
Guideline for Switching Reliability Evaluation procedures for Gallium Nitride Power
Conversion Devices
Ta slovenski standard je istoveten z: prEN IEC 63419:2022
ICS:
29.200 Usmerniki. Pretvorniki. Rectifiers. Convertors.
Stabilizirano električno Stabilized power supply
napajanje
oSIST prEN IEC 63419:2022 en
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.
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oSIST prEN IEC 63419:2022
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oSIST prEN IEC 63419:2022
47/2744/CDV
COMMITTEE DRAFT FOR VOTE (CDV)
PROJECT NUMBER:
IEC 63419 ED1
DATE OF CIRCULATION: CLOSING DATE FOR VOTING:
2021-12-31 2022-03-25
SUPERSEDES DOCUMENTS:
IEC TC 47 : SEMICONDUCTOR DEVICES
SECRETARIAT: SECRETARY:
Korea, Republic of Mr Cheolung Cha
OF INTEREST TO THE FOLLOWING COMMITTEES: PROPOSED HORIZONTAL STANDARD:
TC 91,TC 104
Other TC/SCs are requested to indicate their interest, if any, in
this CDV to the secretary.
FUNCTIONS CONCERNED:
EMC ENVIRONMENT QUALITY ASSURANCE SAFETY
SUBMITTED FOR CENELEC PARALLEL VOTING NOT SUBMITTED FOR CENELEC PARALLEL VOTING
This document is still under study and subject to change. It should not be used for reference purposes.
Recipients of this document are invited to submit, with their comments, notification of any relevant patent rights of which they are
aware and to provide supporting documentation.
TITLE:
Guideline for Switching Reliability Evaluation procedures for Gallium Nitride Power Conversion Devices
PROPOSED STABILITY DATE: 2027
NOTE FROM TC/SC OFFICERS:
This CDV is based upon JEDEC document JEP180 (title: Guideline for Switching Reliability Evaluation procedures for
Gallium Nitride Power Conversion Devices) and is circulated according to the IEC fast-track procedure (see F.2 of
ISO/IEC Directives, Part 1, 2021).
This document is proposed by the US National Committee. TC 47 / WG 8 at the October 2021 meeting approved the
document for fast-track procedure and was presented to TC 47 Plenary at the October 2021 Plenary. TC 47 Secretariat
has reviewed and approved the circulation of the CDV according to the fast-track procedure.
This document is allocated to TC 47 / WG 8 and the project leader is Dr Stephanie Watts Butler.
This document is also of interest to TC 47/WG 5.
Copyright © 2021 International Electrotechnical Commission, IEC. All rights reserved. It is permitted to download this electronic
file, to make a copy and to print out the content for the sole purpose of preparing National Committee positions. You may not copy
or "mirror" the file or printed version of the document, or any part of it, for any other purpose without permission in writing from IEC.
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1 CONTENTS
2
3 FOREWORD . 4
4 INTRODUCTION . 6
5 1 Scope . 8
6 2 Normative references . 8
7 3 Terms, definitions, symbols and abbreviated terms . 8
8 4 Description of test elements . 9
9 4.1 Objectives of stress testing for switching reliability . 9
10 4.2 Technology DUTs and product DUTs . 10
11 4.3 Stressors and associated lifetime acceleration factors . 10
12 4.4 Test vehicles, product vehicles, and stress test beds . 10
13 4.5 Measurements, monitoring, and control . 11
14 4.6 Sample sizes . 12
15 4.7 Failure criteria . 12
16 5 The switching locus curve and its usage . 12
17 5.1 The switching locus curve . 12
18 5.2 Obtaining broad switching reliability coverage . 14
19 6 Developing lifetime models for switching stress . 15
20 6.1 General . 15
21 6.2 Overall methodology . 16
22 6.3 Lifetime model . 17
23 6.4 Model functions . 17
24 6.5 Prediction of GaN switch lifetime . 17
25 7 Dynamic High Temperature Operating Life (DHTOL) test . 18
26 7.1 General . 18
27 7.2 DUT type . 18
28 7.3 Stress test bed . 18
29 7.4 Procedure . 18
30 7.5 Stress conditions . 19
31 8 References . 21
32 ANNEX A (Informative) Obtaining parameter space for accelerated life test with
33 switching stress . 22
34 Annex B (informative) Example experiment sequence for obtaining times-to-failure and
35 lifetime models . 23
36 ANNEX C (Informative) Examples of models and expressions for lifetime . 25
37 C.1 References . 26
38
39 Figure 1 — Simplified explanation of the approach for assuring GaN product reliability.
40 It consists of three key aspects as shown. The approach is not intended to be
41 restrictive, as is described in the text . 7
42 Figure 2 — Simplified examples of switching locus plots for DUT operation in circuits . 13
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43 Figure 3 — HTRB is a one-dimensional example of a harsher stress covering a range of
44 milder operating conditions. . 14
45 Figure 4 — Stress-testing at a more stressful switching locus (solid lines) covers a
46 range of use-cases at less-stressful switching loci (dashed lines). Slew rate or transition
47 time information needs to be provided for meaningful comparisons. . 15
48 Figure 5 — Synopsis of methodology for obtaining wearout models based on switching
49 accelerated tests with one stressor varied at a time and its wearout model obtained from
50 the desired failure fraction . 16
51 Figure 6 — An example of the DHTOL turn-on hard-switching locus, along with a typical
52 less-harsh application-use case . 20
53 Figure B.1 — A figure to illustrate how the independence of stressors to failure-creation
54 can be validated. First, two sets stressors are used to get the acceleration models and
55 then one or more different stress conditions are used to for validating the model. . 24
56
57 Table 1 — Attributes of the two types of stress test beds . 11
58 Table 2 — DHTOL recommendations . 18
59 Table 3 — Best-practice DHTOL conditions . 19
60 Table C.1 — Some expressions for time to failure for various wearout processes in
61 MOSFETs. . 25
62
63
64
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65 INTERNATIONAL ELECTROTECHNICAL COMMISSION
66 ____________
67
68 GUIDELINE FOR SWITCHING RELIABILITY EVALUATION PROCEDURES
69 FOR GALLIUM NITRIDE POWER CONVERSION DEVICES
70
71 FOREWORD
72 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
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80 Organization for Standardization (ISO) in accordance with conditions determined by agreement between the two
81 organizations.
82 2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
83 consensus of opinion on the relevant subjects since each technical committee has representation from all
84 interested IEC National Committees.
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90 transparently to the maximum extent possible in their national and regional publications. Any divergence
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92 the latter.
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101 Publications.
102 8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
103 indispensable for the correct application of this publication.
104 9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
105 patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
106 IEC 63419 has been prepared by IEC technical committee 47: Semiconductor devices. It is an
107 International Standard.
108 This standard is based upon JEP180. It is used with permission of the copyright holder, JEDEC
109 Solid State Technology Association
110 The text of this International Standard is based on the following documents:
Draft Report on voting
XX/XX/FDIS XX/XX/RVD
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111
112 Full information on the voting for its approval can be found in the report on voting indicated in
113 the above table.
114 The language used for the development of this International Standard is English.
115 This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
116 accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available
117 at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
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119 The committee has decided that the contents of this document will remain unchanged until the
120 stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to
121 the specific document. At this date, the document will be
122 • reconfirmed,
123 • withdrawn,
124 • replaced by a revised edition, or
125 • amended.
126
IMPORTANT – The "colour inside" logo on the cover page of this document indicates
that it contains colours which are considered to be useful for the correct
understanding of its contents. Users should therefore print this document using a
colour printer.
127
128
129
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130 INTRODUCTION
131 This document is intended for use by GaN product suppliers and related power electronic
132 industries. It provides guidelines for evaluating the switching reliability of GaN power switches
133 and assuring their reliable use in power conversion applications. It is applicable to planar
134 enhancement-mode, depletion-mode, GaN integrated power solutions and cascode GaN power
135 switches.
136 Gallium Nitride (GaN) power switches are important devices for high-efficiency, small form-
137 factor power conversion applications. Current GaN power switches are based upon the planar
138 High Electron Mobility Transistor (HEMT), which is a Field-Effect Transistor (FET). The switch
139 can be a discrete enhancement or depletion-mode GaN FET, a GaN FET in combination with a
140 silicon transistor forming a cascode and/or co-packaged with silicon control electronics. It can
141 also be a GaN power FET with integrated GaN electronics. During operation, all power devices
142 experience switching stress for which the reliability needs to be evaluated and lifetimes
143 assured.
144 For many silicon power conversion products, operational robustness is often validated by a
145 combination of technology and product-level tests, e.g., Hot Carrier Injection (HCI) [1],
146 Unclamped Inductive Switching (UIS) [2], high-temperature operating life (HTOL) [3]. Individual
147 silicon tests do not necessarily validate operation under actual-use conditions of power
148 conversion products, which simultaneously involve high power transfer through the device, high
149 slew rates, and hot-carrier effects. Each addresses different aspects, and over the years they
150 have been developed to work well together. These tests are either not applicable or have not
151 been comprehensively specified for GaN switches. For example, the HCI test relies on a body
152 contact that is not available in GaN FETs and the UIS test takes the device into avalanche,
153 which is not recommended for GaN FETs. The GaN industry has therefore been conducting
154 switching reliability testing to assure the reliability and robustness of GaN switches [4]-[8], both
155 at the technology level and in application.
156 The industry and research community now need to work towards standardizing the methodology for
157 assuring both the switching reliability of the technology platform and the robustness of GaN switches for
158 use in a broad class of power management applications. Typically, standards lag technology
159 introduction because there needs to be substantial public knowledge of failure modes and mechanisms
160 before a standards document can be published. This takes time because confidential information needs
161 to be de-classified and new knowledge discovered. It is, however, desirable for the industry to develop
162 common approaches sooner, so that customers can readily evaluate the technology options available.
163 The goal of this document is to present guidelines for a common approach, and to accelerate progress
164 towards the future standard.
165 A common approach for power management needs to consider many aspects. Power conversion
166 involves different modes of operation, e.g., hard and soft-switching, the usage of the power switch in
167 many different topologies, and the interaction of the switch with other system components. The
168 approach also needs to detect failure modes of interest to the power electronics industry, e.g., lower
169 efficiency from an increase in on-resistance [7]. It also needs to consider the limitations and strengths of
170 classes of boards and hardware in conducting the stress-testing needed. Finally, the approach needs to
171 assure broad coverage, so as not to introduce unnecessary burden on the industry.
172 This document provides a common approach for assuring that GaN products are reliable in power
173 conversion applications. It provides guidelines for broad coverage, addresses the detection of relevant
174 failure modes, provides guideline stress-test procedures, and proposes common ways to collect and
175 present data. The approach is broken down into guidelines for the three key aspects as shown in
176 Figure 1.
177 1) A procedure for obtaining broad coverage by classifying the switching stress stimuli with
178 their switching loci and explaining the use of a harsher stress condition to cover a milder
179 use-case condition.
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180 2) A procedure for obtaining the switching lifetime of the technology platform. This involves
181 performing accelerated life testing with a suitable type of GaN die or core switch to
182 generate a model.
183 3) A procedure for validating reliable operation under application-use conditions by running
184 parts in an application environment using stress conditions that, if passing, would assure
185 reliable operation for a broad range of use-conditions.
186
187 Figure 1 — Simplified explanation of the approach for assuring GaN product reliability. It
188 consists of three key aspects as shown. The approach is not intended to be restrictive,
189 as is described in the text
190
191 The approach is not intended to be restrictive. It takes into account the strengths and limitations of
192 boards, hardware, and components, while also recognizing the need to not introduce unnecessary
193 burden on the industry. It does not restrict additional testing, larger sample sizes, and stress conditions
194 with higher acceleration. It also does not restrict the use of boards and device types. For instance,
195 lifetime determination can be made using more complex boards or GaN switches by verifying that the
196 complexity does not mask the acceleration of relevant failure mechanisms. Conversely simpler boards
197 can be used to assure application-use reliability by providing collateral material showing robustness to
198 operating modes not tested.
199 The core of this guideline is organized into four clauses, with clauses 5-7 reflective of the aspects of
200 Figure 1.
201 – Clause 4 gives general guidance for selecting test devices, test circuits and developing test
202 plans.
203 – Clause 5 provides an approach for broad coverage by using the switching locus curve.
204 – Clause 6 gives the procedure for obtaining wearout models and device lifetime.
205 – Finally, clause 7 provides guidance on validating reliable operation of GaN switches in
206 power conversion applications.
207
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208 1 Scope
209 This publication presents guidelines for evaluating the switching reliability of GaN power
210 switches. It is applicable to planar enhancement-mode, depletion-mode, GaN integrated power
211 solutions and cascode GaN power switches. It covers the following aspects:
212 a) An approach for broad coverage, using the switching locus to represent switching stress in
213 a standardized manner.
214 b) The development of a lifetime model, based upon the type of application switching locus.
215 c) The validation of reliable operation under application-use conditions.
216 The publication will result in common methods for representing, evaluating and modeling the
217 switching stress on GaN power switches, and ensuring their reliable operation in an
218 application.
219 2 Normative references
220 JEDEC JEP173, Dynamic ON-Resistance Test Method Guidelines for GaN HEMT based Power
221 Conversion Devices, Version 1.0, January 2019
222 To add: upon publication: IEC 63284 ED1, Semiconductor devices – Reliability test method by inductive
223 load switching for gallium nitride transistors
224 3 Terms, definitions, symbols and abbreviated terms
225 No terms and definitions are listed in this document. ISO and IEC maintain terminological
226 databases for use in standardization at the following addresses:
227 • IEC Electropedia: available at http://www.electropedia.org/
228 • ISO Online browsing platform: available at http://www.iso.org/obp
229
Symbol or Abbreviation Name or term
R Drain to Source Resistance of DUT in ON-state
DS(ON)
VT Threshold Voltage
i Drain current of the DUT, time varying
D
vDS Drain to Source Voltage of DUT, time varying
ID Drain current in on-state of DUT
V Drain to Source Voltage of DUT
DS
I Drain current parameter to represent the switching stress
DP
VDP Drain voltage parameter to represent the switching stress
MTTF Mean Time To Failure for a set of stress conditions
ttf Times To Failure
EA Activation Energy
TJ Junction Temperature of DUT
T Case Temperature of DUT
C
Thermal resistance from device junction to case
RθJC
f Switching Frequency
SW
D Duty cycle
tr Rise Time of VDS while switching
tf Fall Time of VDS while switching
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Symbol or Abbreviation Name or term
fv, i, T, etc Acceleration function for given stressor
AF Acceleration Factor
K1, K2, K3, K4 Constants in empirical acceleration models
GaN Gallium Nitride
HEMT High Electron Mobility Transistor
FET Field Effect Transistor
HTOL High Temperature Operating Life
UIS Unclamped Inductive Switching
HCI Hot Carrier Injection
DOE Design of Experiments
SALT Switching Accelerated Life Test
DHTOL Dynamic High Temperature Operating Life
DUT Device Under Test
PCB Printed Circuit Board
HTRB High Temperature Reverse Bias
ZCS Zero Current Switched
ZVS Zero Voltage Switched
230
231 4 Description of test elements
232 4.1 Objectives of stress testing for switching reliability
233 There are two classes of stress tests recommended in this guideline: Switching Accelerated
234 Life Test (Switching-ALT or SALT) and Dynamic High-Temperature Operating-Life (DHTOL)
235 test.
236 For an accelerated lifetime test such as SALT, stress conditions are typically chosen such that
237 there will be wearout failures in the test timeframe. Failures are needed to allow the plotting of
238 failure distributions, e.g., Weibull, lognormal, etc. Wearout models are obtained using these
239 distributions and allow calculation of the device lifetime for application-use conditions. Further
240 details about lifetime determination using SALT are provided in clause 6.
241 For DHTOL, stress conditions are chosen to represent the most stringent mission profile so as
242 to cover all different application use cases, as described further in clauses 5 and 7. DHTOL
243 conditions are typically not chosen to stress till wearout, and it is expected that there will be no
244 failures in the test timeframe. Industry best-practice conditions are used in cases where GaN-
245 specific knowledge is not yet available. An example of best-practice conditions in use for
246 silicon discrete power FETs is the application of stress at 80% of the device rating (or absolute
247 maximum voltage), or at 100% of the maximum recommended voltage (if specified) and the
248 maximum recommended temperature for 1000h.
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249 4.2 Technology DUTs and product DUTs
250 Technology DUTs are GaN devices representative of the GaN technology platform and
251 therefore well suited for accelerated lifetime testing (SALT) and obtaining wearout models. For
252 cases where other components form a core part of the switch, the entire switch may be chosen
253 as a technology DUT for verification that relevant wearout and failure processes for the
254 complete switch are accelerated for lifetime determination. Examples include MOSFETs in
255 cascodes or an integrated GaN device. Lifetime testing involves highly accelerated stress, so it
256 is preferable the DUT has only failure modes native to the technology platform. The DUT die
2
257 size needs to be large enough (e.g., active area > 1mm ) to assure that both temperature
258 increase from self-heating and switching nonuniformity aspects are addressed. The technology
259 DUT should also include core layout aspects needed in the design of a product, e.g.,
260 terminations. When reporting results, either the active area of the GaN die or the R of the
DS(ON)
261 switch should be specified, e.g., 190 mΩ, 130 mΩ, etc. [5], [6].
262 Product DUTs should be the final GaN product in order to replicate the effects of the
263 interaction of multiple possible components and the package used for DHTOL. Product DUTs
264 are not limited to the discrete GaN device, but can be an integrated cascode, co-packaged
265 driver product, or a full GaN IC.
266 4.3 Stressors and associated lifetime acceleration factors
267 There are several variables of interest for investigation and analysis of switching devices:
268 a) Voltage applied across it
269 b) Current flowing through it
270 c) Junction temperature during switching
271 d) Switching frequency
272 e) Duty cycle
273 f) Fall time or slew rate
274 g) Rise time or slew rate
275 It has been shown that the factors affecting lifetime are the voltage, current, and the junction
276 temperature [5], [6]. The role of the other factors has not been established, but they are
277 considered relevant parameters and could potentially affect lifetime. It is therefore
278 recommended to note the values of all the factors when publishing switching locus curves and
279 related reliability information.
280 4.4 Test vehicles, product vehicles, and stress test beds
281 A test vehicle is a simple circuit with appropriate components and layout for subjecting DUTs to
282 one or more well-defined stress modes. The use of test vehicles is in accordance with
283 JESD94B [9], which states, “…a test vehicle may be preferable since the actual product
284 complexity may mask intrinsic failure mechanisms…”
285 A test vehicle for accelerated life testing (SALT) should be designed to subject the device to
286 greater voltage, current, and temperature than the device would experience under normal use
287 conditions. It should apply the relevant switching stress modes for wearout testing without
288 introducing extraneous failure modes. Examples of test circuits for generating hard, soft, and
289 resistive switching transitions are given in t
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