Status
Not Published
Public Enquiry End Date
30-Nov-2026
Technical Committee
I11 - Imaginarni 11
Current Stage
4020 - Public enquire (PE) (Adopted Project)
Start Date
07-Oct-2026
Due Date
24-Feb-2027

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oSIST prEN IEC 62228-5:2026 is the Slovenian standard draft for EMC evaluation of Ethernet transceiver integrated circuits, published by SIST as an identical adoption of prEN IEC 62228-5:2026. It specifies test and measurement methods for Ethernet transceivers under network conditions, including conducted and radiated RF emission, RF immunity, impulse immunity, and ESD. The document is aimed at engineers, labs, quality teams, and buyers who need a common way to test or compare Ethernet transceiver ICs.

What does oSIST prEN IEC 62228-5:2026 specify?

oSIST prEN IEC 62228-5:2026 specifies how to evaluate the EMC performance of Ethernet transceiver ICs in application-like conditions, using a minimal network for active tests and a single transceiver for unpowered ESD tests. The main body gives the shared test framework, and the annexes add the Ethernet-system-specific details.

The document applies to transceivers for these Ethernet systems: 10BASE-T1S, 100BASE-T1, 100BASE-TX, 1000BASE-T1, 2.5G/5G/10GBASE-T1, and 1000BASE-RH. It focuses on RF disturbances, impulses, and ESD as they affect the transceiver pins used in the application.

AnnexWhat it covers
ASpecific test definitions and requirements for 10BASE-T1S transceiver
BSpecific test definitions and requirements for 100BASE-T1 transceiver
CSpecific test definitions and requirements for 100BASE-TX transceiver
DSpecific test definitions and requirements for 1000BASE-T1 transceiver
ESpecific test definitions and requirements for 2.5G/5G/10GBASE-T1 transceiver
FSpecific test definitions and requirements for 1000BASE-RH transceiver
GGeneral test circuits for electrical and optical Ethernet transceivers
HTest circuit boards for functional tests and single-transceiver configuration
IRecommended limits for automotive applications
JCharacterization of common mode chokes (CMC) for EMC evaluation
KCharacterization of ESD suppression devices for EMC evaluation

What are the key requirements of oSIST prEN IEC 62228-5:2026?

The core requirement in oSIST prEN IEC 62228-5:2026 is to evaluate Ethernet transceiver EMC under defined application conditions, using the standard test configurations, signals, failure criteria, and boards from the main clauses and the relevant annex for the Ethernet type being tested. In practice, the same device may need several separate test cases if it supports more than one Ethernet system.

Clause 4 sets the overall approach. It says the common definitions are in the main body, while the detailed test settings and limits for each Ethernet type are given in Annex A to Annex F. That matters because a lab can use one framework while still applying the correct type-specific setup.

Clause 5 defines the operating and test conditions. It covers supply and ambient conditions, normal and low power operation, BIN definition, test configuration, communication signals, evaluation criteria, and DUT-specific information. This is the part a lab uses to make sure the device is in the right mode before applying stress.

A practical point in Clause 4 is that the document distinguishes between testing in a transceiver network and testing a single transceiver IC. Networked tests are used for conducted RF emission, RF immunity, impulse immunity, powered ESD, and radiated tests. Unpowered ESD is done on a separate single-device setup because the purpose is damage evaluation, not functional operation.

The document uses named EMC methods rather than generic stress tests. Clause 6 covers:

  • conducted RF emission by the 150 ohm direct coupling method
  • conducted RF immunity by Direct Power Injection (DPI)
  • impulse immunity by non-synchronous transient injection
  • radiated RF emission and radiated RF immunity with stripline or GTEM-cell methods
  • Electrostatic Discharge (ESD) testing by contact discharge

That matters in practice because the test method determines the equipment, the coupling network, and the interpretation of the result.

For functional tests, the document requires the DUT to be verified in proper operation before each test case. The tests then search for malfunction and determine an immunity threshold or an accepted status class. In plain terms, the result is not just pass or fail - it is also the disturbance level where the transceiver begins to misbehave.

The annexes tailor the same approach to each Ethernet type. They define the operation modes, BINs, coupling ports, signal conditions, and evaluation criteria for that transceiver family. If a transceiver supports more than one Ethernet system, each supported system is tested separately.

Annexes G and H are important for real-world testing. They provide the circuit drawings and test boards used to build soldered, application-like test fixtures. That helps labs avoid artifacts from sockets and makes results easier to compare.

Annex I gives recommended limits for automotive applications. Annexes J and K move beyond the transceiver itself and characterize the interface components in the MDI path, especially the CMC and the ESD suppression device.

What terms does oSIST prEN IEC 62228-5:2026 define?

Device Under Test (DUT) is the Ethernet transceiver IC being evaluated, including any product-specific EMC-relevant pins that the application uses.

Direct Power Injection (DPI) is the conducted RF immunity method used to couple RF disturbance into the transceiver network and observe whether the device keeps working.

Electrostatic Discharge (ESD) is the contact-discharge test family used for both powered and unpowered evaluation of transceiver robustness.

Common Mode Choke (CMC) is the interface component characterized in Annex J for parasitic capacitance, mixed-mode S-parameters, saturation behavior, and ESD damage.

Transmission Line Pulse (TLP) is the pulse-based method used in Annex J to measure CMC saturation behavior under fast current and voltage stress.

Who uses oSIST prEN IEC 62228-5:2026?

oSIST prEN IEC 62228-5:2026 is used by semiconductor manufacturers, IC designers, EMC test laboratories, and validation engineers who need to measure or compare Ethernet transceiver EMC performance. It is also relevant for quality managers and technical buyers who review test evidence for transceiver ICs, especially when the device is used in automotive or other demanding applications.

System integrators who place Ethernet transceiver cells inside EAS, SBCs, or ASICs also use it, because the document says those embedded implementations should follow the PHY test approach with suitable adaptation. Procurement and supplier-quality teams can use the test report structure to check whether the right method and configuration were used.

What changed in oSIST prEN IEC 62228-5:2026 from the previous edition?

This draft supersedes 47A/1211/CD and 47A/1219A/CC. The document also notes that comments on 47A/1211/CD were reviewed and resolved before SC47A moved the project to the CDV stage.

Which standards are used with oSIST prEN IEC 62228-5:2026?

  • IEC 62228-1 - gives the general conditions and definitions for EMC evaluation of transceivers.
  • IEC 61967-1, IEC 61967-2, IEC 61967-4, IEC 61967-8 - provide the IC emission measurement methods used for conducted and radiated emission testing.
  • IEC 62132-1, IEC 62132-2, IEC 62132-4, IEC 62132-8 - provide the IC immunity measurement methods used for conducted and radiated immunity testing.
  • IEC 62215-3 - provides the non-synchronous transient injection method used for impulse immunity.
  • ISO 7637-2 - provides the transient pulse framework used for impulse testing.
  • ISO 10605 - provides the contact-discharge ESD method used for powered and unpowered ESD testing.
  • ISO/IEC/IEEE 8802-3 and ISO/IEC/IEEE 8802-3:2021/AMD 5:2021 - define the Ethernet physical layer systems covered by the standard.
  • CISPR 16-1-1 - defines measurement apparatus and receiver requirements for EMC measurements.
  • EIA-198-1 - supports component classification for ceramic dielectric capacitors used in the test networks.

What does the oSIST prEN IEC 62228-5:2026 document contain?

The document contains the shared test framework in Clauses 4 to 7, plus type-specific annexes for each Ethernet family. It includes test configurations, operating modes, coupling networks, test signals, failure criteria, and report content requirements. It also contains circuit diagrams and board layouts for functional testing, along with figures showing the setups for conducted RF emission, conducted RF immunity, impulse immunity, radiated RF testing, and ESD.

Annexes J and K add more specialized measurement methods. They include procedures and formulas for parasitic capacitance, mixed-mode S-parameters, TLP-based saturation checks, discharge-current measurements, and damage evaluation of CMCs and ESD suppression devices. The document therefore serves both as a test method standard and as a technical reference for building the corresponding fixtures and documentation.

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Effective Date
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Effective Date
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Frequently Asked Questions

oSIST prEN IEC 62228-5:2026 is a draft published by the Slovenian Institute for Standardization (SIST). Its full title is "Integrated circuits - EMC evaluation of transceivers - Part 5: Ethernet transceivers". This standard covers: Integrated circuits - EMC evaluation of transceivers - Part 5: Ethernet transceivers

Integrated circuits - EMC evaluation of transceivers - Part 5: Ethernet transceivers

oSIST prEN IEC 62228-5:2026 is classified under the following ICS (International Classification for Standards) categories: 31.200 - Integrated circuits. Microelectronics; 33.100.01 - Electromagnetic compatibility in general. The ICS classification helps identify the subject area and facilitates finding related standards.

oSIST prEN IEC 62228-5:2026 has the following relationships with other standards: It is inter standard links to SIST EN IEC 62228-5:2021, SIST EN IEC 62228-5:2021/oprA1:2023. Understanding these relationships helps ensure you are using the most current and applicable version of the standard.

oSIST prEN IEC 62228-5:2026 is available in PDF format for immediate download after purchase. The document can be added to your cart and obtained through the secure checkout process. Digital delivery ensures instant access to the complete standard document.

Standards Content (Sample)


SLOVENSKI STANDARD
01-november-2026
Integrirana vezja - Vrednotenje elektromagnetne združljivosti (EMC) oddajnikov-
sprejemnikov - 5. del: Ethernet oddajniki-sprejemniki
Integrated circuits - EMC evaluation of transceivers - Part 5: Ethernet transceivers
Integrierte Schaltungen - Bewertung der elektromagnetischen Verträglichkeit von Sende-
Empfangsgeräten - Teil 5: Ethernet-Sende-Empfangsgerät
Circuits intégrés - Evaluation de la CEM des émetteurs-récepteurs - Partie 5: Emetteurs-
récepteurs ethernet
Ta slovenski standard je istoveten z: prEN IEC 62228-5:2026
ICS:
31.200 Integrirana vezja, Integrated circuits.
mikroelektronika Microelectronics
33.100.01 Elektromagnetna združljivost Electromagnetic compatibility
na splošno in general
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

47A/1226/CDV
COMMITTEE DRAFT FOR VOTE (CDV)

PROJECT NUMBER:
IEC 62228-5 ED2
DATE OF CIRCULATION: CLOSING DATE FOR VOTING:
2026-10-02 2026-12-25
SUPERSEDES DOCUMENTS:
47A/1211/CD, 47A/1219A/CC
IEC SC 47A : INTEGRATED CIRCUITS
SECRETARIAT: SECRETARY:
Japan Mr Yoshinori FUKUBA
OF INTEREST TO THE FOLLOWING COMMITTEES: HORIZONTAL FUNCTION(S):

ASPECTS CONCERNED:
Electromagnetic Compatibility
SUBMITTED FOR CENELEC PARALLEL VOTING NOT SUBMITTED FOR CENELEC PARALLEL VOTING
Attention IEC-CENELEC parallel voting
The attention of IEC National Committees, members of
CENELEC, is drawn to the fact that this Committee Draft
for Vote (CDV) is submitted for parallel voting.
The CENELEC members are invited to vote through the
CENELEC online voting system.
This document is still under study and subject to change. It should not be used for reference purposes.
Recipients of this document are invited to submit, with their comments, notification of any relevant patent rights of
which they are aware and to provide supporting documentation.
Recipients of this document are invited to submit, with their comments, notification of any relevant “In Some
Countries” clauses to be included should this proposal proceed. Recipients are reminded that the CDV stage is
the final stage for submitting ISC clauses. (SEE AC/22/2007 OR NEW GUIDANCE DOC).

TITLE:
Integrated circuits - EMC evaluation of transceivers - Part 5: Ethernet transceivers

PROPOSED STABILITY DATE: 2032
NOTE FROM TC/SC OFFICERS:
All comments on 47A/1211/CD have been reviewed and resolved. SC47A has decided to proceed to
the CDV stage.
download this electronic file, to make a copy and to print out the content for the sole purpose of preparing National
Committee positions. You may not copy or "mirror" the file or printed version of the document, o r any part of it,
for any other purpose without permission in writing from IEC.

Link to Committee Draft for Vote (CDV) online document:
Click here
How to access
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Committee’s (NMC) comments. The project draft may be found further down this document.

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IEC CDV 62228-5 ED2 © IEC 2026

CONTENTS
CONTENTS . 1
FOREWORD . 14
1 Scope . 16
2 Normative references . 16
3 Terms, definitions and abbreviated terms . 17
3.1 Terms and definitions. 17
3.2 Abbreviated terms . 18
4 General . 20
5 Test and operating conditions . 21
5.1 Supply and ambient conditions . 21
5.2 Test operation modes . 22
5.2.1 General . 22
5.2.2 Transceiver configuration for normal operation mode . 22
5.2.3 Transceiver configuration for low power mode . 22
5.3 Definition of BIN. 22
5.4 Test configuration . 24
5.4.1 General configuration for transceiver network . 24
5.4.2 General configuration for single transceiver . 26
5.4.3 Transceiver network tests - coupling ports and networks for conducted
tests . 26
5.4.4 Single transceiver tests - coupling ports and networks . 28
5.5 Test communication and signals . 29
5.5.1 General . 29
5.5.2 Test signals for normal operation mode . 30
5.5.3 Test signals for low power mode . 30
5.6 Evaluation criteria . 30
5.6.1 General . 30
5.6.2 Evaluation criteria for functional operation modes . 30
5.6.3 Evaluation criteria in unpowered condition after exposure to
disturbances . 31
5.6.4 Status classes . 32
5.7 DUT specific information . 32
6 Test and measurement . 33
6.1 Emission of conducted RF disturbances . 33
6.1.1 Test method . 33
6.1.2 Test setup . 33
6.1.3 Test procedure and parameters . 34
6.2 Immunity to conducted RF disturbances . 34
6.2.1 Test method . 34
6.2.2 Test setup . 34
6.2.3 Test procedure and parameters . 35
6.3 Immunity to impulses . 37
6.3.1 Test method . 37
6.3.2 Test setup . 37
6.3.3 Test procedure and parameters . 38
6.4 Emission of radiated RF disturbances . 39
6.4.1 Test method . 39
IEC CDV 62228-5 ED2 © IEC 2026

6.4.2 Test setup . 39
6.4.3 Test procedure and parameters . 40
6.5 Immunity to radiated RF disturbances . 40
6.5.1 Test method . 40
6.5.2 Test setup . 40
6.5.3 Test procedure and parameters . 42
6.6 Electrostatic Discharge (ESD) . 43
6.6.1 Test method . 43
6.6.2 Test setup . 43
6.6.3 Test procedure and parameters . 49
7 Test report . 50
Annex A (normative) Specific test definitions and requirements for 10BASE-T1S
transceiver . 51
A.1 General . 51
A.2 Test operation modes . 51
A.3 BIN definition . 51
A.4 Test configuration . 52
A.5 Coupling ports and networks for conducted tests . 53
A.6 Test communication and signals . 55
A.7 Evaluation criteria for functional operation modes . 56
A.8 Test setups and requirements . 59
A.8.1 Conducted RF emission . 59
A.8.2 Conducted RF immunity. 60
A.8.3 Transient immunity . 63
A.8.4 Radiated RF emission . 64
A.8.5 Radiated RF immunity . 64
A.8.6 ESD . 65
Annex B (normative) Specific test definitions and requirements for 100BASE-T1
transceiver . 66
B.1 General . 66
B.2 Test operation modes . 66
B.3 BIN definition . 66
B.4 Test configuration . 66
B.5 Coupling ports and networks for conducted tests . 67
B.6 Test requirements . 67
B.6.1 Conducted RF emission . 67
B.6.2 Conducted RF immunity. 68
B.6.3 Transient immunity . 70
B.6.4 Radiated RF emission . 71
B.6.5 Radiated RF immunity . 71
B.6.6 ESD . 72
Annex C (normative) Specific test definitions and requirements for 100BASE-TX
transceiver . 73
C.1 General . 73
C.2 Test operation modes . 73
C.3 BIN definition . 73
C.4 Test configuration . 73
C.5 Coupling ports and networks for conducted tests . 73
C.6 Test requirements . 74
IEC CDV 62228-5 ED2 © IEC 2026

C.6.1 Conducted RF emission . 74
C.6.2 Conducted RF immunity. 75
C.6.3 Transient immunity . 76
C.6.4 Radiated RF emission . 77
C.6.5 Radiated RF immunity . 78
C.6.6 ESD . 78
Annex D (normative) Specific test definitions and requirements for 1000BASE-T1
transceiver . 80
D.1 General . 80
D.2 Test operation modes . 80
D.3 BIN definition . 80
D.4 Test configuration . 80
D.5 Coupling ports and networks for conducted tests . 81
D.6 Test requirements . 81
D.6.1 Conducted RF emission . 82
D.6.2 Conducted RF immunity. 82
D.6.3 Transient immunity . 84
D.6.4 Radiated RF emission . 85
D.6.5 Radiated RF immunity . 86
D.6.6 ESD . 86
Annex E (normative) Specific test definitions and requirements for 2.5G/5G/10GBASE-
T1 transceiver . 88
E.1 General . 88
E.2 Test operation modes . 88
E.3 BIN definition . 88
E.4 Test configuration . 88
E.5 Coupling ports and networks for conducted tests . 89
E.6 Test requirements . 89
E.6.1 Conducted RF emission . 89
E.6.2 Conducted RF immunity. 90
E.6.3 Transient immunity . 92
E.6.4 Radiated RF emission . 93
E.6.5 Radiated RF immunity . 93
E.6.6 ESD . 94
Annex F (normative) Specific test definitions and requirements for 1000BASE-RH
transceiver . 95
F.1 General . 95
F.2 Test operation modes . 95
F.3 BIN definition . 96
F.4 Test configuration . 96
F.5 Coupling ports and networks for conducted tests . 99
F.6 Test communication and signals . 99
F.7 Evaluation criteria for functional operation modes . 99
F.8 Test requirements . 99
F.8.1 Conducted RF emission . 99
F.8.2 Conducted RF immunity. 100
F.8.3 Transient immunity . 101
F.8.4 Radiated RF emission . 102
F.8.5 Radiated RF immunity . 103
IEC CDV 62228-5 ED2 © IEC 2026

F.8.6 ESD . 104
Annex G (normative) Ethernet test circuits . 105
G.1 General . 105
G.2 Test circuit for electrical Ethernet transceivers for functional tests . 105
G.2.1 Test circuit for Ethernet transceivers for conducted functional tests . 105
G.2.2 Test circuit for Ethernet transceivers for radiated functional tests . 112
G.3 Test circuit for optical Ethernet transceiver tests . 113
G.3.1 Test circuit for optical Ethernet transceivers for conducted functional
tests . 113
G.3.2 Test circuit for optical Ethernet transceivers for conducted and radiated
functional tests . 115
G.3.3 Test circuit for stand-alone FOT tests . 116
G.4 Test circuit for Ethernet transceivers for unpowered ESD test . 117
Annex H (normative) Test circuit boards . 120
H.1 General . 120
H.2 Test circuit board for electrical Ethernet transceivers for functional tests . 120
H.2.1 Test circuit board for conducted functional tests of electrical Ethernet
transceiver. 120
H.2.2 Test circuit board for radiated functional tests of electrical Ethernet
transceiver. 124
H.3 Test circuit board for optical Ethernet transceiver for functional tests . 126
H.3.1 Test circuit board for optical Ethernet transceivers for conducted
functional tests . 126
H.3.2 Test circuit board for optical Ethernet transceivers for conducted and
radiated functional tests. 126
H.3.3 Test circuit board for stand-alone FOT tests . 127
H.4 Test circuit board for single transceiver configuration. 127
Annex I (informative) Examples for test limits for Ethernet transceiver in automotive
application . 129
I.1 General . 129
I.2 Emission of conducted RF disturbances . 129
I.3 Immunity to conducted RF disturbances . 131
I.4 Immunity to impulses . 134
I.5 Emission of radiated RF disturbances . 134
I.6 Immunity to radiated RF disturbances . 135
Annex J (informative) Characterization of common mode chokes for EMC evaluation of
Ethernet transceivers . 137
J.1 General . 137
J.2 Recommended tests . 137
J.2.1 General . 137
J.2.2 Measurement of parasitic capacitance . 138
J.2.3 142
J.2.4 Mixed mode S-parameter measurement . 142
J.2.5 ESD damage . 149
J.2.6 Saturation test at RF disturbances . 152
J.2.7 Saturation test at ESD . 155
J.2.8 TDR measurement of differential mode impedance . 159
Annex K (informative) Characterization of ESD suppression devices for EMC
evaluation of Ethernet transceivers . 161
K.1 General . 161
IEC CDV 62228-5 ED2 © IEC 2026

K.2 Recommended tests . 162
K.2.1 General . 162
K.2.2 Measurement of parasitic capacitance . 162
K.2.3 Mixed mode S-parameter measurement . 166
K.2.4 ESD damage . 172
K.2.5 ESD discharge current measurement . 175
K.2.6 Test of unwanted clamping effect at RF immunity tests . 180
Bibliography . 184

Figure 1 – Minimum MDI interface test network (Min-BIN) . 23
Figure 2 – Standard MDI interface test network (Std-BIN) . 23
Figure 3 – Optimized MDI interface test network (Opt-BIN) . 23
Figure 4 – General test configuration for tests in transceiver network for conducted
tests . 24
Figure 5 – General test configuration for tests in transceiver network for radiated tests . 25
Figure 6 – General test configuration for unpowered ESD test . 26
Figure 7 – Transceiver network tests - coupling ports and networks . 27
Figure 8 – Coupling ports and networks for unpowered ESD tests . 29
Figure 9 – Principle drawing of the maximum deviation on an I-V characteristic . 32
Figure 10 – Test setup for measurement of conducted RF disturbances. 33
Figure 11 – Test setup for DPI tests . 35
Figure 12 – Test setup for impulse immunity tests . 37
Figure 13 – Test setup for measurement of radiated RF emission . 39
Figure 14 – Test setup for radiated RF immunity tests . 41
Figure 15 – Test setup for powered ESD tests - principle arrangement . 44
Figure 16 – Test setup for powered ESD tests - stimulation and monitoring . 45
Figure 17 – Test setup for unpowered ESD tests - principle arrangement . 46
Figure 18 – Test setup for unpowered ESD tests - stimulation and monitoring for
function validation pre and post ESD test . 48
Figure A.1 – General test configuration for 10BASE-T1S transceiver tests in
transceiver network for conducted tests . 53
Figure A.2 – Transceiver network tests - CP1 coupling ports and network definition for
10BASE-T1S transceiver . 54
Figure A.3 – Test communication signal combination TX-PMD1 for 10BASE-T1S PMD
transceiver emission tests . 56
Figure A.4 – Combined test signal definition TX-PMD2 for 10BASE-T1S PMD
transceiver immunity tests . 56
Figure A.5 – Test setup for DPI distortion test . 60
Figure F.1 – Arrangement of 1000BASE-RH transceiver IC and a separate FOT . 95
Figure F.2 – Arrangement of 1000BASE-RH transceiver IC with an integrated FOT . 95
Figure F.3 – Alternative test configuration for tests of 1000BASE-RH transceivers in
transceiver network using POF for conducted and radiated tests . 96
Figure F.4 – General test configuration for stand-alone FOT tests . 97
Figure F.5 – Test setup for standalone FOT test . 98
Figure G.1 – General drawing of the circuit diagram of test network for xBASE-T1
Ethernet transceivers for functional test using conducted test methods . 107
IEC CDV 62228-5 ED2 © IEC 2026

Figure G.2 – General drawing of the circuit diagram of test network for 10BASE-T1S
PMD Ethernet transceivers for functional test using conducted test methods . 110
Figure G.3 – General drawing of the circuit diagram of test network for 100BASE-TX
Ethernet transceivers for functional test using conducted test methods . 111
Figure G.4 – General drawing of the circuit diagram of test network for xBASE-T1
Ethernet transceivers for functional test using radiated RF test methods . 112
Figure G.5 – General drawing of the circuit diagram of test network for 1000BASE-RH
Ethernet transceivers for functional test using conducted test methods . 114
Figure G.6 – General drawing of the circuit diagram of alternative test network for
1000BASE-RH Ethernet transceivers for functional test using conducted and radiated
test methods . 116
Figure G.7 – General drawing of the circuit diagram stand-alone FOT tests . 117
Figure G.8 – General drawing of the circuit diagram for ESD tests of xBASE-T1
Ethernet transceiver in unpowered mode . 118
Figure H.1 – Example of functional conducted test board for Ethernet transceiver ICs
up to 1 Gbit/s communication rate (100BASE-T1) . 120
Figure H.2 – Example of functional conducted test board for Ethernet transceiver ICs
with more than 1 Gbit/s communication rate (10GBASE-T1) . 121
Figure H.3 – Example of return loss for functional conducted test board for Ethernet
transceiver ICs with more than 1 Gbit/s communication rate (10GBASE-T1) . 122
Figure H.4 – Example of insertion loss for functional conducted test board for Ethernet
transceiver ICs with more than 1 Gbit/s communication rate (10GBASE-T1) . 122
Figure H.5 – Example of CP1 common mode coupling function for functional conducted
test board for Ethernet transceiver ICs with more than 1 Gbit/s communication rate
(10GBASE-T1) . 123
Figure H.6 – Example of powered ESD test board for Ethernet transceivers ICs
(100BASE-T1) . 124
Figure H.7 – Example of functional radiated test board for Ethernet transceiver ICs
(100BASE-T1), top layer (DUT side) . 125
Figure H.8 – Example of functional radiated test board for Ethernet transceiver ICs
(100BASE-T1), bottom layer (external circuitry side) . 125
Figure H.9 – Example of functional conducted test board for optical Ethernet
transceivers (1000BASE-RH) . 126
Figure H.10 – Example of functional radiated test board for optical Ethernet
transceivers (1000BASE-RH), top layer (left, DUT side) and bottom layer (right,
component side) . 127
Figure H.11 – Example of test board for stand-alone FOT tests . 127
Figure H.12 – Example of unpowered ESD test board for Ethernet transceivers ICs
(100BASE-T1), top layer . 128
Figure H.13 – Example of unpowered ESD test board for Ethernet transceivers ICs
(100BASE-T1), bottom layer . 128
Figure I.1 – Example of limits for conducted RF emission - Limit group EMI1-GP -
global pins including MDI . 129
Figure I.2 – Example of limits for conducted RF emission - Limit group EMI2-GP-
global pins that are connected to shielded cables in the application (MDI) . 130
Figure I.3 – Example of limits for conducted RF emission - Limit group EMI1-LS - local
supplies . 130
Figure I.4 – Example of limits for conducted RF immunity for functional status class A
IC
- limit group RF-MDI1-A - MDI. 131
IEC CDV 62228-5 ED2 © IEC 2026

Figure I.5 – Example of limits for conducted RF immunity for functional status class A
IC
- limit group RF-MDI2-A - global pins that are connected to shielded cables in the
application (MDI) . 132
Figure I.6 – Example of limits for conducted RF immunity for functional status class A
IC
- limit group RF-GP1-A - global pins . 132
Figure I.7 – Example of limits for conducted RF immunity for functional status class C
IC
or D - limit group RF-MDI1-C - MDI . 133
IC
Figure I.8 – Example of limits for conducted RF immunity for functional status class C
IC
or D - limit group RF-MDI2-C - global pins that are connected to shielded cables in
IC
the application MDI . 133
Figure I.9 – Example of limits for conducted RF immunity for functional status class C
IC
or D - limit group RF-GP1-C - global pins . 134
IC
Figure I.10 – Example of limits for radiated RF emission for IC stripline with 6,7 mm
active conductor height - limit group RE1 . 135
Figure I.11 – Example of limits for radiated RF immunity - limit group RI1 . 136
Figure J.1 – General electrical drawing of a CMC . 137
Figure J.2 – Test setup for parasitic capacitance of CMC measurement using the VNA
method . 138
Figure J.3 – Example of test board for CMC parasitic capacitance measurement for
VNA method, top layer . 139
Figure J.4 – Port definitions for CMC VNA measurement circuit . 140
Figure J.5 – Test setup for parasitic capacitance measurement of CMC for LCR meter
or impedance analyser method . 140
Figure J.6 – LCR or impedance analyser measurement circuit for CMC . 141
Figure J.7 – Example of parasitic capacitance measurement results for CMC . 142
Figure J.8 – Test setup for S-parameter measurements at CMC . 142
Figure J.9 – Example of test board for 4-port S-parameter measurement of a CMC -
mixed mode, top layer . 143
Figure J.10 – Example of test board for 3-port S-parameter measurement of a CMC -
mixed mode, top layer . 143
Figure J.11 – Port definition for CMC 3-port test board characterization . 144
Figure J.12 – . 144
Figure J.13 – Port definition for 4-port mixed mode measurements . 145
Figure J.14 – Port definition for 3-port mixed mode measurements . 146
Figure J.15 – Recommended characteristics for S , S (RL) for CMC . 147
dd11 dd22
Figure J.16 – Recommended characteristics for S (IL) for CMC . 147
dd21
Figure J.17 – Recommended characteristics for S (CMR) for CMC. 148
cc21
Figure J.18 – Recommended characteristics for S , S (LCL) for CMC . 148
dc11 dc22
Figure J.19 – Recommended characteristics for S , S (DCMR) and S , S
sd21 sd12 ds21 ds12
(CDMR) for CMC . 149
Figure J.20 – Test setup for ESD damage tests at CMC . 150
Figure J.21 – Example of ESD test board for CMC, top layer . 151
Figure J.22 – Test circuit for ESD damage tests of a CMC . 152
Figure J.23 – Test setup for RF saturation measurements at CMC . 153
Figure J.24 – Example of RF saturation / S-parameter test board for CMC, top layer . 154
IEC CDV 62228-5 ED2 © IEC 2026

Figure J.25 – Test circuit for RF saturation tests at CMC . 154
Figure J.26 – Recommended test power levels for RF saturation tests of CMC . 155
Figure J.27 – Test setup for ESD saturation measurements at CMC . 156
Figure J.28 – Example of ESD saturation test board for CMC, top layer . 157
Figure J.29 – Test circuit for ESD saturation tests of a CMC . 157
Figure J.30 – Definition for TLP pulse reference time t . 158
Figure J.31 – Example of ESD saturation tests results of different CMCs . 159
Figure J.32 – Test setup for TDR measurement of a CMC . 159
Figure J.33 – Example of TDR test board for CMC, top layer . 160
Figure J.34 – TDR measurement test circuit for CMC . 160
Figure K.1 – Arrangement of ESD suppression device within the 10BASE-T1S,
100BASE-T1 and 1000BASE-T1 MDI interface . 162
Figure K.2 – Test setup for parasitic capacitance measurement for the VNA method . 163
Figure K.3 – Example of test board parasitic capacitance measurement for the VNA
method, top layer . 164
Figure K.4 – VNA measurement circuit for ESD suppression device . 165
Figure K.5 – Test setup for parasitic capacitance measurement for LCR meter or
impedance analyser method . 165
Figure K.6 – LCR or impedance analyser measurement circuit for ESD suppression
device . 166
Figure K.7 – Test setup for S-parameter measurements at ESD suppression device . 167
Figure K.8 – Example of 4-port S-parameter test board for measurement of ESD
suppression device, top layer . 168
Figure K.9 – Example of 3-port S-parameter test board for measurement of ESD
suppression device , top layer . 168
Figure K.10 – Port definition for ESD suppression device 3-port test board . 169
Figure K.11 – Requirement for 3-port ESD device fixture . 169
Figure K.12 – Port definition for 4-port measurements of ESD suppression device . 170
Figure K.13 – Port definition for 3-port measurements of ESD suppression device . 170
Figure K.14 – Recommended characteristics for S (RL) for ESD suppression device . 171
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