Standard Test Method for Measuring the Depth of Crystal Damage of a Mechanically Worked Silicon Slice Surface by Angle Polishing and Defect Etching

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1.1 This test method describes a technique to measure the depth of damage, on or beneath the surface of silicon wafers prior to any heat treatment of the wafer. Such damage results from mechanical surface treatments such as sawing, lapping, grinding, sandblasting, and shot peening.  
1.2 The principal application of this test method is for determining the depth of damage of the non-polished back surface that has had intentionally added work damage.  
1.3 The measurement is destructive since a specimen is prepared from a section of a silicon wafer.  
1.4 Depth of damage can be measured in the range of 5.0 to 200 [mu]m using this method.  
1.5 For referee purposes, a sampling plan shall be agreed upon between the parties to the test before the tests are started.  
1.6 This standard does not purport to address all of the safety problems, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use. Specific hazard statements are given in Section 9.

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Publication Date
09-May-1998
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ASTM F950-98 - Standard Test Method for Measuring the Depth of Crystal Damage of a Mechanically Worked Silicon Slice Surface by Angle Polishing and Defect Etching
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NOTICE: This standard has either been superseded and replaced by a new version or withdrawn. Contact
ASTM International (www.astm.org) for the latest information.
Designation: F 950 – 98
AMERICAN SOCIETY FOR TESTING AND MATERIALS
100 Barr Harbor Dr., West Conshohocken, PA 19428
Reprinted from the Annual Book of ASTM Standards. Copyright ASTM
Standard Test Method for
Measuring the Depth of Crystal Damage of a Mechanically
Worked Silicon Slice Surface by Angle Polishing and Defect
1
Etching
This standard is issued under the fixed designation F 950; the number immediately following the designation indicates the year of
original adoption or, in the case of revision, the year of last revision. A number in parentheses indicates the year of last reapproval. A
superscript epsilon (e) indicates an editorial change since the last revision or reapproval.
5
1. Scope Spreading Resistance Probe
2.2 SEMI Standard:
1.1 This test method describes a technique to measure the
6
C1 Specifications for Reagents
depth of damage, on or beneath the surface of silicon wafers
prior to any heat treatment of the wafer. Such damage results
3. Terminology
from mechanical surface treatments such as sawing, lapping,
3.1 Definitions of Terms Specific to This Standard:
grinding, sandblasting, and shot peening.
3.1.1 damage—a defect of the crystal lattice of a single
1.2 The principal application of this test method is for
crystal silicon specimen in the form of irreversible deforma-
determining the depth of damage of the non-polished back
tion. The damage is the result of mechanical surface treatments
surface that has had intentionally added work damage.
such as sawing, lapping, grinding, sandblasting, and shot
1.3 The measurement is destructive since a specimen is
peening at room temperature without subsequent heat treat-
prepared from a section of a silicon wafer.
ments.
1.4 Depth of damage can be measured in the range of 5.0 to
3.1.2 damage-free polishing—a method of preparing a sur-
200 μm using this method.
face of a silicon specimen without creating any mechanical
1.5 This test method is intended for use in process control
damage detectable by this method.
where each individual location is resposible to determine the
3.1.3 bevel angle (a)—the smaller of the angles between the
internal repeatability to its satisfaction.
wafer surface and the section plane. (See Fig. 1.)
1.6 This standard does not purport to address all of the
3.1.4 damage depth (T )—the maximum thickness of the
z
safety concerns, if any, associated with its use. It is the
damage region. The damage is revealed by a preferential etch
responsibility of the user of this standard to establish appro-
that removes silicon in the region of the deformation. Prefer-
priate safety and health practices and determine the applica-
ential etching occurs because the chemical potential in the
bility of regulatory limitations prior to use. Specific hazard
region of the deformation is changed by the stress fields
statements are given in Section 9.
associated with the deformation. The depth of damage is
2. Referenced Documents expressed in micrometers.
2.1 ASTM Standards:
4. Summary of Test Method
2
D 1193 Specification for Reagent Water
4.1 A silicon specimen is coated with silicon nitride by a
E 122 Practice for Choice of Sample Size to Estimate a
3 low-pressure plasma method to a minimum thickness of 1 μm.
Measure of Quality for a Lot or Process
The specimen is then beveled at a small angle by a polishing
F 532 Test Methods for Measuring Width of Defects in
technique that produces no additional mechanical damage. The
Optical Surfaces, Using Nomarski Differential Micros-
4 bevel angle is measured. The beveled specimen is etched to
copy
reveal the damage. The length of the damage region is
F 672 Test Method for Measuring Resistivity Profiles Per-
measured from the beveled edge on the beveled section. The
pendicular to the Surface of a Silicon Wafer Using a
depth of damage is then calculated from the relationship
between the measured damage length and the sine of the bevel
angle.
1
This test method is under the jurisdiction of ASTM Committee F-1 on
5. Significance and Use
Electronics and is the direct responsibility of Subcommittee F01.06 on Silicon
Materials and Process Control.
5.1 This test method provides a means for measuring the
Current edition approved May 10, 1998. Published July 1998. Originally
{1
published as F 950 – 85. Last previous edition F 950 – 88(l993) .
2
Annual Book of ASTM Standards, Vol 11.01.
3 5
Annual Book of ASTM Standards, Vol 14.02. Annual Book of ASTM Standards, Vol 10.05.
4 6
Discontinued; see 1993 Annual Book of ASTM Standards, Vol 06.01. Available from the Semiconductor Equipment and Materials International, 805
E. Middlefield Rd., Mountain View, CA 94043.
1

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NOTICE:¬This¬standard¬has¬either¬been¬superceded¬and¬replaced¬by¬a¬new¬version¬or¬discontinued.¬
Contact¬ASTM¬International¬(www.astm.org)¬for¬the¬latest¬
...

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