Semiconductor devices - Mechanical and climatic test methods - Part 41: Standard reliability testing methods of non-volatile memory devices

IEC 60749-41:2020 specifies the procedural requirements for performing valid endurance, retention and cross-temperature tests based on a qualification specification. Endurance and retention qualification specifications (for cycle counts, durations, temperatures, and sample sizes) are specified in JESD47 or are developed using knowledge-based methods such as in JESD94.

Halbleiterbauelemente - Mechanische und klimatische Prüfverfahren - Teil 41: Standardisierte Prüfverfahren für die Zuverlässigkeit von nichtflüchtigen Speicher-Bauelementen

Dispositifs à semiconducteurs - Méthodes d’essais mécaniques et climatiques - Partie 41: Méthodes d’essai normalisées pour la fiabilité des dispositifs à mémoire non volatile

L’IEC 60749-41:2020 spécifie les exigences relatives aux procédures permettant de réaliser des essais valides d’endurance, de conservation de données et à températures opposées, basées sur une spécification de qualification. Les spécifications de qualification des essais d’endurance et de conservation de données (pour les nombres de cycles, durées, températures et tailles d’échantillon) sont données dans le document JESD47 ou sont développées en utilisant des méthodes à base de connaissances, telles que celles données dans le document JESD94.

Polprevodniški elementi - Mehanske in klimatske preskusne metode - 41. del: Standardne metode preverjanja zanesljivosti nehlapnih snovi pomnilniških naprav (IEC 60749-41:2020)

General Information

Status
Published
Drafting Committee
Current Stage
6060 - Document made available
Due Date
04-Sep-2020
Completion Date
04-Sep-2020

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SLOVENSKI STANDARD
SIST EN IEC 60749-41:2020
01-november-2020
Polprevodniški elementi - Mehanske in klimatske preskusne metode - 41. del:
Standardne metode preverjanja zanesljivosti nehlapnih snovi pomnilniških naprav
(IEC 60749-41:2020)
Semiconductor devices - Mechanical and climatic test methods - Part 41: Standard
reliability testing methods of non-volatile memory devices (IEC 60749-41:2020)
Halbleiterbauelemente - Mechanische und klimatische Prüfverfahren - Teil 41:

Standardisierte Prüfverfahren für die Zuverlässigkeit von nichtflüchtigen Speicher-

Bauelementen (IEC 60749-41:2020)

Dispositifs à semiconducteurs - Méthodes d’essais mécaniques et climatiques - Partie

41: Méthodes d’essai normalisées pour la fiabilité des dispositifs à mémoire non volatile

(IEC 60749-41:2020)
Ta slovenski standard je istoveten z: EN IEC 60749-41:2020
ICS:
31.080.01 Polprevodniški elementi Semiconductor devices in
(naprave) na splošno general
SIST EN IEC 60749-41:2020 en

2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

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SIST EN IEC 60749-41:2020
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SIST EN IEC 60749-41:2020
EUROPEAN STANDARD EN IEC 60749-41
NORME EUROPÉENNE
EUROPÄISCHE NORM
September 2020
ICS 31.080.01
English Version
Semiconductor devices - Mechanical and climatic test methods -
Part 41: Standard reliability testing methods of non-volatile
memory devices
(IEC 60749-41:2020)

Dispositifs à semiconducteurs - Méthodes d'essais Halbleiterbauelemente - Mechanische und klimatische

mécaniques et climatiques - Partie 41: Méthodes d'essai Prüfverfahren - Teil 41: Standardisierte Prüfverfahren für

normalisées pour la fiabilité des dispositifs à mémoire non die Zuverlässigkeit von nichtflüchtigen Speicher-

volatile Bauelementen
(IEC 60749-41:2020) (IEC 60749-41:2020)

This European Standard was approved by CENELEC on 2020-08-26. CENELEC members are bound to comply with the CEN/CENELEC

Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration.

Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC

Management Centre or to any CENELEC member.

This European Standard exists in three official versions (English, French, German). A version in any other language made by translation

under the responsibility of a CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the

same status as the official versions.

CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, the Czech Republic,

Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the

Netherlands, Norway, Poland, Portugal, Republic of North Macedonia, Romania, Serbia, Slovakia, Slovenia, Spain, Sweden, Switzerland,

Turkey and the United Kingdom.
European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung
CEN-CENELEC Management Centre: Rue de la Science 23, B-1040 Brussels

© 2020 CENELEC All rights of exploitation in any form and by any means reserved worldwide for CENELEC Members.

Ref. No. EN IEC 60749-41:2020 E
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SIST EN IEC 60749-41:2020
EN IEC 60749-41:2020 (E)
European foreword

The text of document 47/2631/FDIS, future edition 1 of IEC 60749-41, prepared by IEC/TC 47

"Semiconductor devices" was submitted to the IEC-CENELEC parallel vote and approved by

CENELEC as EN IEC 60749-41:2020.
The following dates are fixed:

• latest date by which the document has to be implemented at national (dop) 2021-05-26

level by publication of an identical national standard or by endorsement

• latest date by which the national standards conflicting with the (dow) 2023-08-26

document have to be withdrawn

Attention is drawn to the possibility that some of the elements of this document may be the subject of

patent rights. CENELEC shall not be held responsible for identifying any or all such patent rights.

Endorsement notice

The text of the International Standard IEC 60749-41:2020 was approved by CENELEC as a European

Standard without any modification.
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SIST EN IEC 60749-41:2020
EN IEC 60749-41:2020 (E)
Annex ZA
(normative)
Normative references to international publications
with their corresponding European publications

The following documents are referred to in the text in such a way that some or all of their content

constitutes requirements of this document. For dated references, only the edition cited applies. For

undated references, the latest edition of the referenced document (including any amendments)

applies.

NOTE 1 Where an International Publication has been modified by common modifications, indicated by (mod),

the relevant EN/HD applies.

NOTE 2 Up-to-date information on the latest versions of the European Standards listed in this annex is available

here: www.cenelec.eu.
Publication Year Title EN/HD Year
IEC 60749-6 - Semiconductor devices - Mechanical and EN 60749-6 -
climatic test methods - Part 6: Storage at
high temperature
IEC 60749-23 - Semiconductor devices - Mechanical and EN 60749-23 -
climatic test methods - Part 23: High
temperature operating life
JESD47 - Stress-Test-Driven Qualification of - -
Integrated Circuits
JESD94 - Application Specific Qualification Using - -
Knowledge Based Test Methodology
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SIST EN IEC 60749-41:2020
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SIST EN IEC 60749-41:2020
IEC 60749-41
Edition 1.0 2020-07
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices – Mechanical and climatic test methods –
Part 41: Standard reliability testing methods of non-volatile memory devices
Dispositifs à semiconducteurs – Méthodes d’essais mécaniques
et climatiques –
Partie 41: Méthodes d’essai normalisées pour la fiabilité des dispositifs
à mémoire non volatile
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.080.01 ISBN 978-2-8322-8640-1

Warning! Make sure that you obtained this publication from an authorized distributor.

Attention! Veuillez vous assurer que vous avez obtenu cette publication via un distributeur agréé.

® Registered trademark of the International Electrotechnical Commission
Marque déposée de la Commission Electrotechnique Internationale
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SIST EN IEC 60749-41:2020
– 2 – IEC 60749-41:2020 © IEC 2020
CONTENTS

FOREWORD ........................................................................................................................... 3

INTRODUCTION ..................................................................................................................... 5

1 Scope .............................................................................................................................. 6

2 Normative references ...................................................................................................... 6

3 Terms and definitions ...................................................................................................... 6

4 Apparatus ........................................................................................................................ 9

5 Procedure ........................................................................................................................ 9

5.1 Qualification specifications...................................................................................... 9

5.2 Program/erase endurance ..................................................................................... 10

5.2.1 Test setup ..................................................................................................... 10

5.2.2 Data cycling ................................................................................................... 11

5.2.3 Electrical test verification ............................................................................... 14

5.3 Data retention ....................................................................................................... 14

5.3.1 Data programming ......................................................................................... 14

5.3.2 Electrical testing and pattern verification (excluding any EEPROM

program/erase testing) ................................................................................... 15

5.3.3 Data retention stress ..................................................................................... 15

5.3.4 Electrical testing and pattern verification ....................................................... 15

5.4 Precautions ........................................................................................................... 15

5.5 Measurements ...................................................................................................... 15

5.5.1 Electrical measurements ................................................................................ 15

5.5.2 Required measurements ................................................................................ 15

5.5.3 Measurement conditions ................................................................................ 16

6 Failure criteria and calculation ....................................................................................... 16

6.1 Failure definition ................................................................................................... 16

6.2 Handling of transient failures ................................................................................ 16

6.3 Separation of failures into data errors and device failures ..................................... 16

6.4 Calculation of UBER ............................................................................................. 17

6.4.1 UBER definition calculation............................................................................ 17

6.4.2 Calculation of UBER in the ideal case ............................................................ 17

6.4.3 Calculation of UBER in other cases ............................................................... 18

7 Summary ....................................................................................................................... 18

Annex A (informative) Supplementary test condition ............................................................ 19

Bibliography .......................................................................................................................... 20

Figure 1 – Schematic flow ..................................................................................................... 10

Figure A.1 – Endurance-retention testing model .................................................................... 19

Figure A.2 – Test concept of data retention bake as a function of endurance ........................ 19

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SIST EN IEC 60749-41:2020
IEC 60749-41:2020 © IEC 2020 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
MECHANICAL AND CLIMATIC TEST METHODS –
Part 41: Standard reliability testing methods
of non-volatile memory devices
FOREWORD

1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising

all national electrotechnical committees (IEC National Committees). The object of IEC is to promote

international co-operation on all questions concerning standardization in the electrical and electronic fields. To

this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,

Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC

Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested

in the subject dealt with may participate in this preparatory work. International, governmental and non-

governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely

with the International Organization for Standardization (ISO) in accordance with conditions determined by

agreement between the two organizations.

2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international

consensus of opinion on the relevant subjects since each technical committee has representation from all

interested IEC National Committees.

3) IEC Publications have the form of recommendations for international use and are accepted by IEC National

Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC

Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any

misinterpretation by any end user.

4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications

transparently to the maximum extent possible in their national and regional publications. Any divergence

between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in

the latter.

5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity

assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any

services carried out by independent certification bodies.

6) All users should ensure that they have the latest edition of this publication.

7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and

members of its technical committees and IEC National Committees for any personal injury, property damage or

other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and

expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC

Publications.

8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is

indispensable for the correct application of this publication.

9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of

patent rights. IEC shall not be held responsible for identifying any or all such patent rights.

International Standard IEC 60749-41 has been prepared by IEC technical committee 47:

Semiconductor devices. This standard is based on JEDEC Standard 22-A117. It is used with

permission of the copyright holder, JEDEC Solid State Technology Association.
The text of this International Standard is based on the following documents:
FDIS Report on voting
47/2631/FDIS 47/2643/RVD

Full information on the voting for the approval of this International Standard can be found in

the report on voting indicated in the above table.

This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.

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SIST EN IEC 60749-41:2020
– 4 – IEC 60749-41:2020 © IEC 2020

A list of all parts in the IEC 60749 series, published under the general title Semiconductor

devices – Mechanical and climatic test methods, can be found on the IEC website.

The committee has decided that the contents of this publication will remain unchanged until

the stability date indicated on the IEC website under "http://webstore.iec.ch" in the data

related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.

IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates

that it contains colours which are considered to be useful for the correct

understanding of its contents. Users should therefore print this document using a

colour printer.
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SIST EN IEC 60749-41:2020
IEC 60749-41:2020 © IEC 2020 – 5 –
INTRODUCTION

The stress tests described in this part of IEC 60749 are intended to determine the ability of an

EEPROM integrated circuit or an integrated circuit with an EEPROM module (such as a

microprocessor) to sustain repeated data changes without failure (program/erase endurance)

and to retain data for the expected life of the EEPROM (data retention).

The program/erase endurance and data retention test for qualification and monitoring, using

the parameter levels specified in JESD47, is considered destructive. The data retention stress

can be used as a proxy to replace the high temperature storage life test when the temperature

and time meet or exceed qualification requirements. Cross-temperature testing for writing and

reading across the data sheet temperature range can be considered when there are

demonstrated sensitivities for programming at low and reading at high temperatures or vice

versa. Lesser test parameter levels (e.g., of temperature, number of cycles, retention bake

duration) can be used for screening as long as these parameter levels have been verified by

the device manufacturer to be nondestructive; this can be performed anywhere from wafer

level to finished device.
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SIST EN IEC 60749-41:2020
– 6 – IEC 60749-41:2020 © IEC 2020
SEMICONDUCTOR DEVICES –
MECHANICAL AND CLIMATIC TEST METHODS –
Part 41: Standard reliability testing methods
of non-volatile memory devices
1 Scope

This part of IEC 60749 specifies the procedural requirements for performing valid endurance,

retention and cross-temperature tests based on a qualification specification. Endurance and

retention qualification specifications (for cycle counts, durations, temperatures, and sample

sizes) are specified in JESD47 or are developed using knowledge-based methods such as in

JESD94.
2 Normative references

The following documents are referred to in the text in such a way that some or all of their

content constitutes requirements of this document. For dated references, only the edition

cited applies. For undated references, the latest edition of the referenced document (including

any amendments) applies.

IEC 60749-6, Semiconductor devices – Mechanical and climatic test methods – Part 6:

Storage at high temperature

IEC 60749-23, Semiconductor devices – Mechanical and climatic test methods – Part 23: High

temperature operating life
JESD47, Stress-Test-Driven Qualification of Integrated Circuits

JESD94, Application Specific Qualification Using Knowledge Based Test Methodology

3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.

ISO and IEC maintain terminological databases for use in standardization at the following

addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
3.1
cross-temperature test
CTT

data read verification across the opposite end of the operating temperature range such that

when programming occurs at low temperature it is properly read at hot temperature or vice

versa
Note 1 to entry: This note applies to the French language only.
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SIST EN IEC 60749-41:2020
IEC 60749-41:2020 © IEC 2020 – 7 –
3.2
cross-temperature test failure
CTTF

data read verification failure across the opposite end of the operating temperature range

where it was programmed
Note 1 to entry: This note applies to the French language only.
3.3
electrically erasable programmable read-only memory
EEPROM
reprogrammable read-only memory in which the cells at each address can be erased
electrically and reprogrammed electrically

Note 1 to entry: The term EEPROM in this document includes all such memories, including flash EEPROM

integrated circuits and embedded memory in integrated circuits such as Erasable Programmable Logic Devices

(EPLDs) and microcontrollers. Destructive-read memories such as ferroelectric memories, in which the read

operation re-writes the data in the memory cells, are beyond the scope of this document.

Note 2 to entry: This note applies to the French language only.
3.4
data pattern
mix of several 1s and 0s in the memory and their physical or logical positions

Note 1 to entry: A device can be single-bit-per-cell (SBC), meaning that one physical memory cell stores a "0" or

a "1", or multiple-bits-per-cell (MBC), meaning that one cell stores typically two bits of data: "00", "01", "10", or "11".

In some MBC memories, the two bits represent logically-adjacent bit-pairs in each byte of data. For example, for

2 bits per cell, a byte containing binary data 10110001 would correspond to four physical cells with data 2301 in

base-four logic. In other MBC memories, the two bits can represent bits in entirely different address locations. For

an SBC memory a physical checkerboard pattern consists of alternating 0s and 1s, with each 0 surrounded by 1s

on either side and above and below; a logical checkerboard pattern consists of data bytes AAH or 55H in which

each 0 is logically adjacent to 1s. In some qualifications only logical positions are known.

3.5
endurance

ability of a reprogrammable read-only memory to withstand data rewrites and still comply with

applicable specifications

Note 1 to entry: EEPROM device specifications often require an erase step before reprogramming data; in this

case a data rewrite includes both erase and programming steps, which together are called a program/erase cycle.

Direct-write memories allow data to be written directly over old, without an erase; in this case the use of the

generic term "program/erase cycle" will refer to a single rewrite with no erase. For single-bit-per-cell (SBC)

memories that require an erase step, one program/erase cycle consists of programming cells (typically to "0") and

then erasing ("1"). For the comparable multiple-bits-per-cell (MBC) case, a cycle would consist of programming

cells (to "0", "1", or "2" for two bits per cell) and then erasing ("3" for two bits per cell).

Note 2 to entry: Endurance cycling consists of performing multiple rewrites in succession, and the data pattern or

patterns for these rewrites must be chosen. There is no one data pattern or set of patterns that is worst-case for all

failure mechanisms. For example, for floating-gate memories a fully programmed pattern is worst-case for charge

transfer, but a physical checkerboard pattern is worst-case for spurious programming of adjacent cells, and a

mostly erased pattern can be worst-case for mechanisms related to erase-preconditioning algorithms. For MBC

memories, programming to the highest state is worst-case for charge transfer, but intermediate-state cells can

experience more programming time and also have less sensing margin. Finally, in some memories, the margin of a

cell is influenced by the data states of the physically adjacent cells.
3.6
endurance failure
failure caused by endurance cycling

Note 1 to entry: An endurance failure occurs if, as a result of program/erase cycling, an EEPROM fails to

complete the program or erase operations within the datasheet-specified times or if it fails to meet any of its other

datasheet requirements. A program operation that results in incorrect data being stored in the device counts as an

endurance failure. However, if an error-management method such as an error-correction code is built into the

device or specified to be applied by the system, then failure is taken to occur only if the error is not properly

managed by the specified method.
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SIST EN IEC 60749-41:2020
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Note 2 to entry: Certain EEPROMS are specified to operate with either internal or external bad-block

management system (BBM). When the BBM system detects an endurance failure it directs the data to another

(spare) block and removes the address of the failing block from an appropriate address table. An endurance failure

of such product is taken to occur when a pre-set number of spare blocks of the product had been consumed within

that product datasheet specified cycle count.

Note 3 to entry: A number of distinct failure mechanisms are responsible for endurance failures, and in general

these are accelerated in different ways by temperature and other adjustable qualification parameters such as

cycling delay between cycles. For example, in floating-gate memories, failure may be caused by charge trapping

(normally accelerated by lower temperatures and/or shorter cycling delay) in the charge transfer dielectric or by

oxide rupturing (normally accelerated by higher temperatures) in the transfer dielectric or in peripheral dielectrics.

3.7
failure

loss of the ability of a component to meet the electrical or physical performance specifications

that (by design or testing) it was intended to meet

Note 1 to entry: The term "failure" is often qualified by an adjective describing the type of failure. For example, a

component is a functional failure if it fails to function and a parametric failure if it functions but does not meet a

datasheet specification for a parameter such as power consumption. Endurance and retention failures are defined

in 3.6 and 3.9.

Note 2 to entry: Failures can be firm or transient. For the purpose of this standard, a firm failure is a component

that fails sometime during a reliability stress and continues to fail at the final test at the end of that same stress. A

transient failure is a component that fails during a reliability stress but passes in the final test at the end of that

stress.
3.8
data retention
retention
ability of EEPROM cell to retain data over time

Note 1 to entry: The one-word term "retention" is usually used when context ensures that no confusion is likely;

otherwise, the full term "data retention" is used.

Note 2 to entry: The term data retention can refer to the ability of a device to retain data in the unbiased state,

but the term will sometimes be used to include the ability to retain data under bias. The term "disturb" refers

unambiguously to the ability of an EEPROM cell to retain data over time under bias. For example, read disturb

refers to the ability of an EEPROM cell to retain data after being read a given number of times. A detailed

discussion of disturbs is beyond the scope of this document.

Note 3 to entry: Retention stressing consists of writing a data pattern into a device and then verifying that the

pattern is intact after a specified time at a specified temperature. There is no single data pattern that is worst-case

for all retention mechanisms, cell designs, or process architectures. There are generally some failure mechanisms

which primarily affect programmed cells and some which primarily affect erased cells, and there are also failure

mechanisms which depend on the data in adjacent cells.
3.9
data retention failure
retention failure

change of stored data by one bit or more detected when the device is read according to

applicable specifications after an extended period of time following the previous write

Note 1 to entry: The short-term "retention failure" is usually used when context ensures that no confusion is likely,

otherwise the full term "data retention failure" is used.

Note 2 to entry: It is necessary to distinguish whether or not retention failure was caused by charge loss or some

other mechanism. Endurance cycling with shorter cycling delay between cycles might induce apparent bit change

or pseudo-bit-flip.

Note 3 to entry: If an error-management method such as an error-correction-code is built into the device or

specified to be applied by the system, then failure is taken to occur only if the error is not properly managed by the

specified method.

Note 4 to entry: A number of distinct failure mechanisms are responsible for retention failures, and in general

these are accelerated in different ways by temperature and other adjustable qualification parameters. For example,

in floating-gate memories, failure can occur due to defects that allow charge to leak through the transfer dielectric

or by the detrapping of charge in the transfer dielectric; the former can be weakly accelerated or even decelerated

by high temperature, and the latter can be highly temperature-accelerated.
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IEC 60749-41:2020 © IEC 2020 – 9 –
3.10
uncorrectable bit-error rate
UBER

metric for the rate of occurrence of data errors, equal to the bit error rate (BER) after applying

any specified error-correction method

Note 1 to entry: The uncorrectable bit error rate is calculated from the following equation:

k (1)
where k is UBER,
e is the cumulative number of data errors and
b is the cumulative number of bits read

For non-error-corrected devices, any data bit in error counts as a data error. For error-corrected devices, any

codeword or sector (as defined in the product data sheet) returning incorrect data after applying the s

...

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