FprEN IEC 61189-3-302:2025
(Main)Test methods for electrical materials, printed boards and other interconnection structures and assemblies - Part 3-302: Detection of plating defects in unpopulated circuit boards by computed tomography (CT)
Test methods for electrical materials, printed boards and other interconnection structures and assemblies - Part 3-302: Detection of plating defects in unpopulated circuit boards by computed tomography (CT)
IEC 61189-3-302:2025 describes a method for the detection of plating defects in unpopulated circuit boards using computed tomography (CT). This document is applicable to non-destructive testing of metallized holes.
Prüfverfahren für Elektromaterialien, Leiterplatten und andere Verbindungsstrukturen und Baugruppen – Teil 3-302: Computertomographisches Verfahren (CT) zur Detektion von Metallisierungsfehlern in unbestückten Leiterplatten
Méthodes d’essai pour les matériaux électriques, les cartes imprimées et autres structures d’interconnexion et ensembles – Partie 3-302: Détection des défauts de métallisation dans les cartes de circuits imprimés nus par tomographie informatisée (TI)
L’IEC 61189-3-302:2025 décrit la méthode de détection des défauts de métallisation des cartes de circuits imprimés nus par tomographie informatisée (TI). Le présent document s’applique aux essais non destructifs des trous métallisés.
Preskusne metode za električne materiale, tiskana vezja in druge povezovalne strukture in sestave - 3-302. del: Odkrivanje napak pri galvanizaciji golih tiskanih vezij z računalniško tomografijo (CT)
General Information
Standards Content (Sample)
SLOVENSKI STANDARD
oSIST prEN IEC 61189-3-302:2024
01-december-2024
Preskusne metode za električne materiale, tiskana vezja in druge povezovalne
strukture in sestave - 3-302. del: Odkrivanje napak pri galvanizaciji golih tiskanih
vezij z računalniško tomografijo (CT)
Test methods for electrical materials, printed board and other interconnection structures
and assemblies - Part 3-302: Detection of plating defects in unpopulated circuit boards
by computed tomography (CT)
Méthodes d’essai pour les matériaux électriques, les cartes imprimées et autres
structures d’interconnexion et ensembles - Partie 3-302: Détection des défauts de
métallisation dans les cartes de circuits imprimés nus par tomographie informatisée (TI)
Ta slovenski standard je istoveten z: prEN IEC 61189-3-302:2024
ICS:
31.180 Tiskana vezja (TIV) in tiskane Printed circuits and boards
plošče
oSIST prEN IEC 61189-3-302:2024 en
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.
oSIST prEN IEC 61189-3-302:2024
oSIST prEN IEC 61189-3-302:2024
91/1973/CDV
COMMITTEE DRAFT FOR VOTE (CDV)
PROJECT NUMBER:
IEC 61189-3-302 ED1
DATE OF CIRCULATION: CLOSING DATE FOR VOTING:
2024-10-04 2024-12-27
SUPERSEDES DOCUMENTS:
91/1941/CD, 91/1969/CC
IEC TC 91 : ELECTRONICS ASSEMBLY TECHNOLOGY
SECRETARIAT: SECRETARY:
Japan Mr Osamu IKEDA
OF INTEREST TO THE FOLLOWING COMMITTEES: HORIZONTAL FUNCTION(S):
ASPECTS CONCERNED:
SUBMITTED FOR CENELEC PARALLEL VOTING NOT SUBMITTED FOR CENELEC PARALLEL VOTING
Attention IEC-CENELEC parallel voting
The attention of IEC National Committees, members of
CENELEC, is drawn to the fact that this Committee Draft for
Vote (CDV) is submitted for parallel voting.
The CENELEC members are invited to vote through the
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This document is still under study and subject to change. It should not be used for reference purposes.
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clauses. (SEE AC/22/2007 OR NEW GUIDANCE DOC).
TITLE:
Test methods for electrical materials, printed board and other interconnection structures and assemblies -
Part 3-302: Detection of plating defects in unpopulated circuit boards by computed tomography (CT)
PROPOSED STABILITY DATE: 2030
NOTE FROM TC/SC OFFICERS:
electronic file, to make a copy and to print out the content for the sole purpose of preparing National Committee positions. You
may not copy or "mirror" the file or printed version of the document, or any part of it, for any other purpose without permis sion
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oSIST prEN IEC 61189-3-302:2024
91/1973/CDV – 2 – IEC CDV 61189-3-302 © IEC 2024
1 CONTENTS
3 FOREWORD . 4
4 1. Scope . 6
5 2. Normative references . 6
6 3. Terms and definitions . 6
7 4. Test principle . 6
8 5. Equipment . 7
9 5.1 X-ray CT scanner . 7
10 5.1.1X-ray source system . 7
11 Table 1- Reference examples of focal size and spatial resolution correspondence
12 for source focus size . 7
13 5.1.2 Mechanical Scanning Systems . 7
14 5.1.3 Detector Systems . 7
15 Table 2— Reference examples of the imaging resolution of the detector system
16 corresponding to the imaging field of view. 7
17 5.1.4 Shielding Facilities . 7
18 5.2 Software Systems . 7
19 6. Test environment . 8
20 7. Test the steps . 8
21 7.1 Equipment Preparation . 8
22 7.2 Sample clamping . 8
23 7.3 Parameter Settings . 8
24 7.3.1 X-ray sources . 8
25 7.3.2 Scanning Methods . 8
26 7.3.3 Scanning the Field of View . 8
27 7.3.4 Number of Frames Scanned . 9
28 7.3.5 Scan Time . 9
29 7.4 Scanning . 9
30 7.5 Image Reconstruction . 9
31 7.5.1 3D Reconstruction . 9
32 7.5.2 Image Quality . 9
33 7.5.3 Visualization . 9
34 7.5.4 Image Analysis and data processing . 9
35 7.5.5 Image Saving . 9
36 8. Reports . 10
37 8.1 Basic Information . 10
38 8.2 Device Information . 10
39 8.3 Sample Information . 10
40 8.4 Sweep Parameters . 10
41 8.5 Measurement results . 10
42 A.1 Typical image of plating voids . 11
43 A.2 Typical image of blind via copper filling defects . 11
44 A.3 Typical image of nodulation . 11
45 A.4 Typical image of plating folds . 12
46 A.5 Typical image of interlayer coincidence . 12
oSIST prEN IEC 61189-3-302:2024
IEC CDV 61189-3-302 © IEC 2024 - 3 - 91/1973/CDV
47 B.1 Void Identification . 13
48 B.1.1 Principle . 13
49 B.1.2 Via . 13
50 B.1.3 Fill hole . 13
51 B.2 Statistical analysis . 14
52 B.2.1 Number of voids . 14
53 B.2.2 Calculated the maximum length of the voids/board thickness ratio . 14
54 B.2.3 Calculated filled holes void rate. 14
55 Bibliography . 16
57 Figure 1 –Typical process of CT analysis . 6
58 Figure A.1 –plating voids . 11
59 Figure A.2 –blind via copper filling defects . 11
60 Figure A.3 –Plating nodulation . 12
61 Figure A.4 –Plating folds . 12
62 Figure A.5 –Interlayer coincidenceAnnex B . 12
63 Figure B.1 –Plating holes voids recognition image . 13
64 Figure B.2 –Identify the void along the board thickness direction . 13
65 Figure B.3 –Fill holes voids recognition image . 14
66 Figure B.4 –Microvia void image . 14
68 Table 1- Reference examples of focal size and spatial resolution correspondence for
69 source focus size . 7
70 Table 2— Reference examples of the imaging resolution of the detector system
71 corresponding to the imaging field of view . 7
oSIST prEN IEC 61189-3-302:2024
91/1973/CDV – 4 – IEC CDV 61189-3-302 © IEC 2024
75 INTERNATIONAL ELECTROTECHNICAL COMMISSION
76 ____________
78 TEST METHODS FOR ELECTRICAL MATERIALS,CIRCUIT BOARD AND
79 OTHER INTERCONNECTION STRUCTURES AND ASSEMBLIES-
81 Part 3-302: Detection of plating defects in unpopulated circuit boards by
82 computed tomography (CT)
84 FOREWORD
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