Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries

Applies to CMOS ASIC libraries which contain cell based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification and logic synthesis.The delay calculation method addressed in this standard consists of 1) estimation of wire capacitance 2 ) Delay calculation method based on tablelook-up. With use of DCL and SDF, this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.

General Information

Status
Withdrawn
Publication Date
16-May-2002
Withdrawal Date
31-May-2011
Drafting Committee
Current Stage
WPUB - Publication withdrawn
Completion Date
01-Jun-2011
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IEC 61523-2:2002 - Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries Released:5/17/2002 Isbn:2831863414
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INTERNATIONAL IEC
STANDARD
61523-2
First edition
2002-05
Delay and power calculation standards –
Part 2:
Pre-layout delay calculation specification
for CMOS ASIC libraries
Reference number
Publication numbering
As from 1 January 1997 all IEC publications are issued with a designation in the
60000 series. For example, IEC 34-1 is now referred to as IEC 60034-1.
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edition numbers 1.0, 1.1 and 1.2 refer, respectively, to the base publication, the
base publication incorporating amendment 1 and the base publication incorporating
amendments 1 and 2.
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INTERNATIONAL IEC
STANDARD
61523-2
First edition
2002-05
Delay and power calculation standards –
Part 2:
pre-layout delay calculation specification
for CMOS ASIC libraries
 IEC 2002  Copyright - all rights reserved
No part of this publication may be reproduced or utilized in any form or by any means, electronic or
mechanical, including photocopying and microfilm, without permission in writing from the publisher.
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– 2 – 61523-2  IEC:2002(E)
CONTENTS
Foreword .3
1 Scope and object .5
2 Normative references .5
3 Relations with other companion standards activities .6
4 Terms and definitions .6
5 Pre-layout delay calculation method for CMOS ASIC libraries .7
Annex A (informative)  Four points interpolation .15
Annex B (informative) Three ponts interpolation .17
Annex C (informative) Selection method of interpolation plane .20
Annex D (informative)  Theoretical accuracy comparison between two interpolation
methods .25
Annex E (informative) Application example.31
Annex F (informative) Example of Cn, Ts, Tpd tables by delay calculation language .35

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Two Step Delay Calculation
step 1: Calculate < Input Slew Rate >
step 2: Calculate < Port to Port Propagation Delay;Tpd
by using < Input Slew Rate >

. .
. .
. .

CL0 CL1
Figure 1: CMOS Delay Model & Calculation Steps
5.2. Table Look-Up delay calculation method
The table look-up model of delay calculation specification uses 3 types of table models. First is the
‘Net capacitance table’ (named Cn table). This table is used for ‘load capacitance’ estimation. Second is
‘Input slew rate table’ (named Ts
...

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