Semiconductor devices - Discrete devices - Part 8: Field-effect transistors

IEC 60747-8:2010 gives standards for the following categories of field-effect transistors:
- type A: junction-gate type;
- type B: insulated-gate depletion (normally on) type;
- type C: insulated-gate enhancement (normally off) type.
The main changes with respect to the previous edition are listed below.
a) "Clause 3 Classification" was moved and added to Clause 1.
b) "Clause 4 Terminology and letter symbols" was divided into "Clause 3 Terms and definitions" and "Clause 4 Letter symbols" was amended with additions and deletions.
c) Clause 5, 6 and 7 were amended with necessary additions and deletions.
This publication is to be read in conjunction with IEC 60747-1:2006.

Dispositifs à semiconducteurs - Dispositifs descrets - Partie 8: Transistors à effet de champ

La CEI 60747-8:2010 donne les normes pour les catégories suivantes de transistors à effets de champ:
- type A: type à jonction de grille;
- type B: type à grille isolée à déplétion (appauvrissement) (normalement à l'état passant);
- type C: type à grille isolée à enrichissement (normalement à l'état bloqué).
Les principaux changements par rapport à l'édition précédente sont énumérés ci-dessous.
a) L'Article 3 "Classification" a été déplacé et ajouté à l'Article 1.
b) L'Article 4 "Terminologie et symboles littéraux" a été divisé en Article 3 "Termes et définitions" et Article 4 "Symboles littéraux", ce dernier a été amendé avec des additions et des suppressions.
c) Les Articles 5, 6 et 7 ont été amendés avec les nécessaires additions et suppressions.
Cette publication doit être lue conjointement avec la CEI 60747-1:2006.

General Information

Status
Published
Publication Date
14-Dec-2010
Current Stage
PPUB - Publication issued
Start Date
15-Dec-2010
Completion Date
15-Dec-2010
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IEC 60747-8
Edition 3.0 2010-12
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices – Discrete devices –
Part 8: Field-effect transistors
Dispositifs à semiconducteurs – Dispositifs descrets –
Partie 8: Transistors à effet de champ
IEC 60747-8:2010
---------------------- Page: 1 ----------------------
THIS PUBLICATION IS COPYRIGHT PROTECTED
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---------------------- Page: 2 ----------------------
IEC 60747-8
Edition 3.0 2010-12
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices – Discrete devices –
Part 8: Field-effect transistors
Dispositifs à semiconducteurs – Dispositifs descrets –
Partie 8: Transistors à effet de champ
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
CODE PRIX
ICS 31.080.30 ISBN 978-2-88912-279-0
® Registered trademark of the International Electrotechnical Commission
Marque déposée de la Commission Electrotechnique Internationale
---------------------- Page: 3 ----------------------
– 2 – 60747-8 Ó IEC:2010
CONTENTS

FOREW ORD .................................................................................................................. 6

1 Sc o pe ...................................................................................................................... 8

2 Normative references ................................................................................................ 8

3 Terms and definitions ................................................................................................ 9

3.1 Types of field-effect transistors .......................................................................... 9

3.2 General terms ................................................................................................ 10

3.2.1 Physical regions (of a field-effect transistor)........................................... 10

3.2.2 Functional regions ............................................................................... 11

3.3 Terms related to ratings and characteristics ...................................................... 12

3.4 Conventional used terms ................................................................................ 17

4 Letter symbols ........................................................................................................ 17

4.1 General ......................................................................................................... 17

4.2 Additional general subscripts ........................................................................... 17

4.3 List of letter symbols ...................................................................................... 17

4.3.1 Voltage .............................................................................................. 17

4.3.2 Currents ............................................................................................. 18

4.3.3 Power dissipation ................................................................................ 18

4.3.4 Small-signal parameters ...................................................................... 18

4.3.5 Other parameters ................................................................................ 20

4.3.6 Matched-pair field-effect transistors ...................................................... 21

4.3.7 Inverse diodes integrated in MOSFETs .................................................. 21

5 Essential ratings and characteristics ......................................................................... 22

5.1 General ......................................................................................................... 22

5.1.1 Device categories................................................................................ 22

5.1.2 Multiple-gate devices ........................................................................... 22

5.1.3 Handling precautions ........................................................................... 22

5.2 Ratings (limiting values).................................................................................. 22

5.2.1 Temperatures ..................................................................................... 22

5.2.2 Power dissipation (P )........................................................................ 22

tot

5.2.3 Safe operating area (SOA) for MOSFET only ........................................... 22

5.2.4 Voltages and currents .......................................................................... 23

5.3 Characteristics ............................................................................................... 23

5.3.1 Characteristics for low-frequency amplifier ............................................. 23

5.3.2 Characteristics for high-frequency amplifier ........................................... 25

5.3.3 Characteristics for high and low power switching and chopper ................. 27

5.3.4 Characteristics for low-level amplifier .................................................... 30

5.3.5 Characteristics for voltage-controlled resistor ......................................... 32

5.3.6 Specific characteristics of matched-pair field-effect transistors for

low-frequency differential ..................................................................... 33

6 Measuring methods ................................................................................................ 34

6.1 General ......................................................................................................... 34

6.2 Verification of ratings (limiting values) .............................................................. 34

6.2.1 Voltages and currents .......................................................................... 34

6.2.2 Safe operating area ............................................................................. 40

6.2.3 Avalanche energy ............................................................................... 44

6.3 Methods of measurement ................................................................................ 46

---------------------- Page: 4 ----------------------
60747-8 Ó IEC:2010 – 3 –

6.3.1 Breakdown voltage, drain to source (V ) ....................................... 46

(BR)DS*
6.3.2 Gate-source off-state voltage (V ) (type A and B), gate source
GS(off)

threshold voltage (V ) (type C) ....................................................... 47

GS(th)
6.3.3 Drain leakage current (d.c.) (I )(type C), Drain cut-off current (d.c.)
DS*

(I ) (type A and B) ........................................................................... 48

DSX
6.3.4 Gate cut-off current (I )(type A), Gate-leakage current (I )(type
GS* GS*

B and C) ............................................................................................ 48

6.3.5 (Static) drain-source on-state resistance (r ) or drain-source on-
DS(on)

state voltage (V ) ......................................................................... 49

DS(on)

6.3.6 Switching times (t , t , t , and t ) .................................................. 51

d(on) r d(off) f

6.3.7 Turn-on power dissipation (P ), turn-on energy (per pulse) (E ) ............ 52

on on

6.3.8 Turn-off power dissipation (P ), turn-off energy (per pulse) (E ) ............ 53

off off

6.3.9 Gate charges (Q , Q , Q , Q ) .............................................. 53

G GD GS(th) GS(pl)

6.3.10 Common source short-circuit input capacitance (C ) ............................. 54

iss

6.3.11 Common source short-circuit output capacitance (C ) ........................... 55

oss

6.3.12 Common source short-circuit reverse transfer capacitance (C ) ............. 56

rss

6.3.13 Internal gate resistance (r ) .................................................................. 57

6.3.14 MOSFET forward recovery time (t ) and MOSFET forward recovered

charge (Q ) ......................................................................................... 58

6.3.15 Drain-source reverse voltage (V ) ..................................................... 62

DSR

6.3.16 Small-signal short-circuit output conductance (type A, B and C) (g ) ...... 62

oss
6.3.17 Small-signal short-circuit forward transconductance (types A, B and

C) ...................................................................................................... 65

6.3.18 Noise (types A, B and C) (F, Vn) ........................................................... 67

6.3.19 On-state drain-source resistance (under small-signal conditions)

(r ) .............................................................................................. 68

ds(on)
6.3.20 Channel-case transient thermal impedance (Z ) and thermal
th(j-c)

resistance (R ) of a field-effect transistor ......................................... 69

th(j-c)

7 Acceptance and reliability ........................................................................................ 71

7.1 General requirements ..................................................................................... 71

7.2 Acceptance-defining characteristics ................................................................. 71

7.3 Endurance and reliability tests ......................................................................... 72

7.3.1 High-temperature blocking (HTRB)........................................................ 72

7.3.2 High-temperature gate bias .................................................................. 72

7.3.3 Intermittent operating life (load cycles) .................................................. 72

7.4 Type tests and routine tests ............................................................................ 73

7.4.1 Type tests .......................................................................................... 73

7.4.2 Routine tests ...................................................................................... 73

Bibliography ................................................................................................................. 75

Figure 1 – Basic waveforms to specify the gate charges ................................................... 14

Figure 2 – Integral times for the turn-on energy E and turn-off energy E ....................... 16

on off

Figure 3 – Switching times ............................................................................................ 21

Figure 4 – Circuit diagram for testing of drain-source voltage ............................................ 35

Figure 5 – Circuit diagram for testing of gate-source voltage ............................................. 35

Figure 6 – Circuit diagram for testing of gate-drain voltage ............................................... 36

Figure 7 – Basic circuit for the testing of drain current ...................................................... 37

Figure 8 – Circuit diagram for testing of peak drain current ............................................... 38

Figure 9 – Basic circuit for the testing of reverse drain current of MOSFETs ....................... 38

---------------------- Page: 5 ----------------------
– 4 – 60747-8 Ó IEC:2010

Figure 10 – Basic circuit for the testing of peak reverse drain current of MOSFETs ............. 39

Figure 11 – Circuit diagram for verifing FBSOA ............................................................... 40

Figure 12 – Circuit diagram for verifying RBSOA.............................................................. 41

Figure 13 – Test waveforms for verifying RBSOA ............................................................. 41

Figure 14 – Circuit for testing safe operating pulse duration at load short circuit ................. 42

Figure 15 – Waveforms of gate-source voltage V , drain current I and voltage V
GS D DS

during load short circuit condition SCSOA ....................................................................... 43

Figure 16 – Circuit for the inductive avalanche switching .................................................. 44

Figure 17 – Waveforms of I , V and V during unclamped inductive switching ............... 44

D DS GS

Figure 18 – Waveforms of I , V and V for the non-repetitive avalanche switching ........ 45

D DS GS

Figure 19 – Circuit diagrams for the measurement drain-source breakdown voltage ............ 46

Figure 20 – Circuit diagram for measurement of gate-source off-state voltage and gate-

source threshold voltage ............................................................................................... 47

Figure 21 – Circuit diagram for drain leakage (or off-state) current or drain cut-off

current measurement .................................................................................................... 48

Figure 22 – Circuit diagram for measuring of gate cut-off current or gate leakage

current ........................................................................................................................ 49

Figure 23 – Basic circuit of measurement for on-state resistance ...................................... 50

Figure 24 – On-state resistance ..................................................................................... 50

Figure 25 – Circuit diagram for switching time ................................................................. 51

Figure 26 – Schematic switching waveforms and times ..................................................... 51

Figure 27 – Circuit for determining the turn-on and turn-off power dissipation and/or

energy ......................................................................................................................... 52

Figure 28 – Circuit diagrams for the measurement gate charges........................................ 54

Figure 29 – Basic for the measurement of short-circuit input capacitance ........................... 55

Figure 30 – Basic circuit for measurement of short-circuit output capacitance (C ) ............ 56

oss

Figure 31 – Circuit for measurement of reverse transfer capacitance C .......................... 57

rss

Figure 32 – Circuit for measurement of internal gate resistance ........................................ 58

Figure 33 – Circuit diagram for MOSFET forward recovery time and recovered charge

(Method 1) ................................................................................................................... 59

Figure 34 – Current waveform through MOSFET (Method 1) ............................................. 59

Figure 35 – Circuit diagram for MOSFET forward recovery time and recovered charge

(Method 2) ................................................................................................................... 60

Figure 36 – Current waveform through MOSFET (Method 2) ............................................. 61

Figure 37 – Circuit diagram for the measurement of drain-source reverse voltage ............... 62

Figure 38 – Basic circuit for the measurement of the output conductance g (method 1:

oss

null method) ................................................................................................................. 63

Figure 39 – Basic circuit for the measurement of the output conductance g (method 2:

oss

two-voltmeter method) .................................................................................................. 64

Figure 40 – Circuit for the measurement of short-circuit forward transconductance g

(Method 1: Null method) ................................................................................................ 65

Figure 41 – Circuit for the measurement of forward transconductance g (method 2:

two-voltmeter method) .................................................................................................. 66

Figure 42 – Block diagram for the measurement of equivalent input noise voltage ............... 67

Figure 43 – Circuit for the measurement of equivalent input noise voltage .......................... 67

Figure 44 – Circuit diagram for the measurement of on-state drain-source resistance .......... 68

---------------------- Page: 6 ----------------------
60747-8 Ó IEC:2010 – 5 –

Figure 45 – Circuit diagram ........................................................................................... 69

Figure 46 – Circuit for high-temperature blockings ........................................................... 72

Figure 47 – Circuit for high-temperature gate bias............................................................ 72

Figure 48 – Circuit for intermittent operating life .............................................................. 73

Table 1 – Terms for MOSFET in this standard and the conventional used terms for the

inverse diode integrated in the MOSFET ......................................................................... 17

Table 2 – Acceptance defining characteristics ................................................................. 34

Table 3 – Acceptance-defining characteristics for endurance and reliability tests ................ 71

Table 4 – Minimum type and routine tests for FETs when applicable .................................. 74

---------------------- Page: 7 ----------------------
– 6 – 60747-8 Ó IEC:2010
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
DISCRETE DEVICES –
Part 8: Field-effect transistors
FOREWORD

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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is

indispensable for the correct application of this publication.

9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of

patent rights. IEC shall not be held responsible for identifying any or all such patent rights.

International Standard IEC 60747-8 has been prepared by subcommittee 47E: Discrete

semiconductor devices, of IEC technical committee 47: Semiconductor devices.

This third edition of IEC 60747-8 cancels and replaces the second edition published in 2000.

This third edition constitutes a technical revision.
The main changes with respect to the previous edition are listed below.
a) ”Clause 3 Classification” was moved and added to Clause 1.

b) “Clause 4 Terminology and letter symbols” was divided into “Clause 3 Terms and

definitions” and “Clause 4 Letter symbols” was amended with additions and deletions.

c) Clause 5, 6 and 7 were amended with necessary additions and deletions.
---------------------- Page: 8 ----------------------
60747-8 Ó IEC:2010 – 7 –
The text of this standard is based on the following documents:
FDIS Report on voting
47E/398/FDIS 47E/406/RVD

Full information on the voting for the approval of this standard can be found in the report on

voting indicated in the above table.

This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.

This Part 8 should be used in conjunction with IEC 60747-1:2006.

A list of all the parts in the IEC 60747 series, under the general title Semiconductor devices –

Discrete devices, can be found on the IEC website.

Future standards in this series will carry the new general title as cited above. Titles of existing

standards in this series will be updated at the time of the next edition.

The committee has decided that the contents of this publication will remain unchanged until

the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data

related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
---------------------- Page: 9 ----------------------
– 8 – 60747-8 Ó IEC:2010
SEMICONDUCTOR DEVICES –
DISCRETE DEVICES –
Part 8: Field-effect transistors
1 Scope

This part of IEC 60747 gives standards for the following categories of field-effect transistors:

– type A: junction-gate type;
– type B: insulated-gate depletion (normally on) type;
– type C: insulated-gate enhancement (normally off) type.

Since a field-effect transistor may have one or several gates, the classification shown below

results:
Field-effect devices
(a source, a drain, one or several gates)
Devices with one or Devices with one or
several P channels several N channels
Junction-gate Schottky Insulated-gate Junction-gate Schottky Insulated-gate
devices barrier-gate devices devices barrier-gate devices
devices devices
MESFET MOSFET MESFET MOSFET
MODFET Other insulated- MODFET Other insulated-
HEMT gate FET HEMT gate FET

NOTE 1 Schottky barrier-gate and insulated gate devices include depletion type devices and enhancement type

devices.

NOTE 2 MOSFETs for some applications may not have inverse diode characteristics in the data sheet. Special

circuit element structures to eliminate body diode are under development for such applications. MOSFET

applications such as motor control equipment need to specify the inverse diode characteristics in the MOSFET to

use the inverse diode as a free wheeling diode.

NOTE 3 The graphical symbol only for type C is used in this standard. The standard equally applies for P-channel

and for type A and B devices.
2 Normative references

The following referenced documents are indispensable for the application of this document.

For dated references, only the edition cited applies. For undated references, the latest edition

of the referenced document (including any amendments) applies.
IEC 61340 (all parts), Electrostatics
IEC 60747-1:2006, Semiconductor devices – Part 1: General
---------------------- Page: 10 ----------------------
60747-8 Ó IEC:2010 – 9 –
IEC 60747-7:2000, Semiconductor devices – Part 7: Bipolar transistors

IEC 60749-23:2004, Semiconductor devices – Mechanical and climatic test methods – Part 23:

High temperature operating life

IEC 60749-34, Semiconductor devices – Mechanical and climatic test methods – Part 34:

Power cycling
3 Terms and definitions
For the purpose of this document, the following terms and definitions apply.
3.1 Types of field-effect transistors
3.1.1
N-channel field-effect transistor
field-effect transistor that has one or more N-type conduction channels
3.1.2
P-channel field-effect transistor
field-effect transistor that has one or more P-type conduction channels
3.1.3
junction-gate field-effect transistor
JFET
field-effect transistor in which

– the source and drain regions are connected with each other by the channel region, all

three being of the same conductivity type;

– a gate region adjacent to the channel has the opposite conductivity type, thus forming with

source, channel and drain region
...

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