EN IEC 62878-2-5:2019

Device embedding assembly technology - Part 2-5: Guidelines - Implementation of a 3D data format for device embedded substrate

IEC 62878-2-5:2019 specifies requirements based on XML schema that represents a design data format for device embedded substrate, which is a board comprising embedded active and passive devices whose electrical connections are made by means of a via, electroplating, conductive paste or printing of conductive material. This data format is to be used for simulation (e.g. stress, thermal, EMC), tooling, manufacturing, assembly, and inspection requirements. Furthermore, the data format is used for transferring information among printed board designers, printed board simulation engineer, manufacturers, and assemblers. IEC 62878-2-5:2019 applies to substrates using organic material. It neither applies to the re-distribution layer (RDL) nor to the electronic modules defined as M-type business model in IEC 62421.

Montageverfahren für eingebettete Bauteile - Teil 2-5: Leitfaden - Implementierung eines 3D-Datenformats für Trägermaterial mit eingebetteten Bauteilen

Techniques d’assemblage avec intégration d’appareils - Partie 2-5 : Lignes directrices - Mise en œuvre d’un format de données 3D pour un substrat avec appareils intégrés

L’IEC 62878-2-5:2019 spécifie des exigences fondées sur le schéma XML qui représente un format de données de conception pour le substrat avec appareil(s) intégré(s), c’est-à-dire une carte avec appareil(s) intégré(s) actif(s) ou passif(s) dont les connexions électriques se font au moyen d’un trou de liaison, de galvanoplastie, de pâte conductrice ou d’impression du matériau conducteur. Ce format de données doit être utilisé pour les exigences de simulation (par exemple, contrainte, thermique, compatibilité électromagnétique), d’outillage, de fabrication, d’assemblage et d’examen. De plus, le format de données est utilisé pour le transfert d’informations entre les concepteurs de cartes imprimées, les ingénieurs de simulation des cartes imprimées, les fabricants et les assembleurs. La présente partie de l’IEC 62878 s’applique aux substrats utilisant des matériaux organiques. Elle ne s'applique ni à la couche de redistribution (RDL, re-distribution layer), ni aux modules électroniques définis comme un modèle commercial de type M dans l'IEC 62421.

Substrat z vdelanimi elementi - 2-5. del: Uvajanje 3D podatkovnega formata za substrat z vdelanimi elementi

General Information

• Status: Published
• Publication Date: 07-Nov-2019
• Withdrawal Date: 20-Oct-2022
• ICS: 31.180 - Printed circuits and boards
• ICS: 31.190 - Electronic component assemblies
• Technical Committee: CLC/SR 91 - Electronics assembly technology
• Drafting Committee: IEC/TC 91 - IEC_TC_91
• Current Stage: 6060 - Document made available - Publishing
• Start Date: 08-Nov-2019
• Completion Date: 08-Nov-2019
• Ref Project: SIST EN IEC 62878-2-5:2021 - Device embedded substrate - Part 2-5: Implementation of a 3D data format for device embedded substrate

Standards Content (Sample)

SLOVENSKI STANDARD
01-junij-2021
Substrat z vdelanimi elementi - 2-5. del: Uvajanje 3D podatkovnega formata za
substrat z vdelanimi elementi
Device embedded substrate - Part 2-5: Implementation of a 3D data format for device
embedded substrate
Ta slovenski standard je istoveten z: EN IEC 62878-2-5:2019
ICS:
31.180 Tiskana vezja (TIV) in tiskane Printed circuits and boards
plošče
31.190 Sestavljeni elektronski Electronic component
elementi assemblies
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

EUROPEAN STANDARD EN IEC 62878-2-5

NORME EUROPÉENNE
EUROPÄISCHE NORM
November 2019
ICS 31.180; 31.190
English Version
Device embedding assembly technology - Part 2-5: Guidelines -
Implementation of a 3D data format for device embedded
substrate
(IEC 62878-2-5:2019)
Techniques d’assemblage avec intégration d’appareils - Montageverfahren für eingebettete Bauteile - Teil 2-5:
Partie 2-5 : Lignes directrices - Mise en œuvre d’un format Implementierung eines 3D-Datenformats für Trägermaterial
de données 3D pour un substrat avec appareils intégrés mit eingebetteten Bauteilen
(IEC 62878-2-5:2019) (IEC 62878-2-5:2019)
This European Standard was approved by CENELEC on 2019-10-21. CENELEC members are bound to comply with the CEN/CENELEC
Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration.
Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC
Management Centre or to any CENELEC member.
This European Standard exists in three official versions (English, French, German). A version in any other language made by translation
under the responsibility of a CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the
same status as the official versions.
CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, the Czech Republic,
Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the
Netherlands, Norway, Poland, Portugal, Republic of North Macedonia, Romania, Serbia, Slovakia, Slovenia, Spain, Sweden, Switzerland,
Turkey and the United Kingdom.

European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung
CEN-CENELEC Management Centre: Rue de la Science 23, B-1040 Brussels
© 2019 CENELEC All rights of exploitation in any form and by any means reserved worldwide for CENELEC Members.
Ref. No. EN IEC 62878-2-5:2019 E

European foreword
The text of document 91/1557/CDV, future edition 1 of IEC 62878-2-5, prepared by IEC/TC 91
"Electronics assembly technology" was submitted to the IEC-CENELEC parallel vote and approved by
CENELEC as EN IEC 62878-2-5:2019.
The following dates are fixed:
• latest date by which the document has to be implemented at national (dop) 2020-07-21
level by publication of an identical national standard or by endorsement
• latest date by which the national standards conflicting with the (dow) 2022-10-21
document have to be withdrawn
Attention is drawn to the possibility that some of the elements of this document may be the subject of
patent rights. CENELEC shall not be held responsible for identifying any or all such patent rights.

Endorsement notice
The text of the International Standard IEC 62878-2-5:2019 was approved by CENELEC as a
European Standard without any modification.

IEC 62878-2-5 ®
Edition 1.0 2019-09
INTERNATIONAL
STANDARD
colour
inside
Device embedding assembly technology –

Part 2-5: Guidelines – Implementation of a 3D data format for device embedded

substrate
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 31.180; 31.190 ISBN 978-2-8322-7399-9

– 2 – IEC 62878-2-5:2019 © IEC 2019
CONTENTS
FOREWORD . 5
1 Scope . 7
2 Normative references . 7
3 Terms and definitions . 7
4 Data definition . 10
4.1 Flow chart design of device embedded substrate . 10
4.2 Applicable range . 11
4.2.1 Product . 11
4.2.2 Process . 12
4.3 Features . 13
4.3.1 General . 13
4.3.2 Device embedded substrate structure . 13
4.3.3 SiP interposer structure . 14
4.3.4 Virtual layer description . 15
4.3.5 Terminal structure and embedded device structure including an SiP . 15
4.3.6 Total design data of an SiP and device embedded substrate . 15
4.4 Data description summary . 16
4.4.1 Type of data and structures . 16
4.4.2 File structure . 18
4.5 3D expression . 19
4.5.1 General . 19
4.5.2 Coordinates . 19
4.5.3 Position description . 20
4.5.4 Relation between coordinate origin and board position . 20
4.6 Layer concept . 21
4.7 Substrate data . 21
4.7.1 General . 21
4.7.2 Layer map information . 22
4.7.3 Device arrangement information . 23
4.7.4 Basic figures . 25
4.7.5 Net information . 31
4.7.6 Artwork information . 32
4.7.7 Package information . 32
4.7.8 External port information. 33
4.7.9 Internal port information . 33
4.7.10 User expansion information . 33
4.8 Defined data . 33
4.8.1 General . 33
4.8.2 Layer definition . 33
4.8.3 Land definition . 34
4.8.4 Via definition . 35
4.8.5 Device definition . 36
4.8.6 User expansion definition . 37
5 Data organization and data description based on XML schema . 38
5.1 General . 38
5.2 Data organization of Example 1 . 38
5.3 Data description of layer stack-up . 39

IEC 62878-2-5:2019 © IEC 2019 – 3 –
5.4 Data description of device . 43
5.5 Data organization of layer . 47
5.6 Data description of via . 50
5.7 Data description of land . 51
Bibliography . 53

Figure 1 – Flow chart of design of device embedded substrate . 11
Figure 2 – General structure of device embedded substrate . 12
Figure 3 – Example of device embedded substrate structure. 14
Figure 4 – Examples of SiPs . 14
Figure 5 – Example of virtual layer description . 15
Figure 6 – Terminal structure . 15
Figure 7 – Structure of SiP on a device embedded substrate . 16
Figure 8 – Data structure . 18
Figure 9 – One file structure (recommended) . 19
Figure 10 – Two file structure . 19
Figure 11 – Definition of coordinates . 20
Figure 12 – Position definition . 20
Figure 13 – Relation between coordinates and board position . 21
Figure 14 – Layer concept . 21
Figure 15 – Layer construction . 22
Figure 16 – Simplified layer construction . 23
Figure 17 – Layer definition of pad connection . 24
Figure 18 – Layer definition of via connection . 24
Figure 19 – Rotation direction on X, Y, and Z axes . 25
Figure 20 – Point . 26
Figure 21 – Area . 27
Figure 22 – Lines . 27
Figure 23 – Letters . 28
Figure 24 – Letter shape . 28
Figure 25 – Bonding wire information . 29
Figure 26 – Semi-sphere . 29
Figure 27 – Truncated pyramid . 30
Figure 28 – Via . 30
Figure 29 – Device definition . 31
Figure 30 – Group .
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