Ferrite cores - Guide on the limits of surface irregularities - Part 5: Planar-cores

IEC 60424-5:2009 gives guidance on allowable limits of surface irregularities applicable to planar-cores in accordance with the relevant generic specification. This standard is considered as a sectional specification useful in the negotiation between ferrite core manufacturers and users about surface irregularities.

Ferritkerne - Leitfaden für Grenzwerte von sichtbaren Beschädigungen der Kernoberfläche - Teil 5: Planarkerne

Noyaux ferrites - Guide relatif aux limites des irrégularités de surface - Partie 5: Noyaux planaires

La CEI 60424-5:2009 donne des lignes directrices relatives aux limites admissibles pour les irrégularités de surface applicables aux noyaux planaires conformément à la spécification générique applicable. La présente norme est considérée comme une spécification intermédiaire utile dans les négociations entre fabricants et utilisateurs de noyaux de ferrite concernant les irrégularités de surface.

Feritna jedra - Vodilo o omejitvah površinskih neregularnosti - 5. del: Planarna jedra (IEC 60424-5:2009)

General Information

Status
Withdrawn
Publication Date
19-May-2009
Withdrawal Date
31-Mar-2012
Current Stage
9960 - Withdrawal effective - Withdrawal
Start Date
21-May-2023
Completion Date
21-May-2023

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SLOVENSKI STANDARD
01-julij-2009
Feritna jedra - Vodilo o omejitvah površinskih neregularnosti - 5. del: Planarna
jedra (IEC 60424-5:2009)
Ferrite cores - Guide on the limits of surface irregularities - Part 5: Planar-cores (IEC
60424-5:2009)
Ferritkerne - Leitfaden für Grenzwerte von sichtbaren Beschädigungen der
Kernoberfläche - Teil 5: Planarkerne (IEC 60424-5:2009)
Noyaux ferrites - Guide relatif aux limites des irrégularités de surface - Partie 5: Noyaux
planaires (CEI 60424-5:2009)
Ta slovenski standard je istoveten z: EN 60424-5:2009
ICS:
29.100.10 Magnetne komponente Magnetic components
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

EUROPEAN STANDARD
EN 60424-5
NORME EUROPÉENNE
May 2009
EUROPÄISCHE NORM
ICS 29.100.10
English version
Ferrite cores -
Guide on the limits of surface irregularities -
Part 5: Planar-cores
(IEC 60424-5:2009)
Noyaux ferrites -  Ferritkerne -
Guide relatif aux limites Leitfaden für Grenzwerte von sichtbaren
des irrégularités de surface - Beschädigungen der Kernoberfläche -
Partie 5: Noyaux planaires Teil 5: Planarkerne
(CEI 60424-5:2009) (IEC 60424-5:2009)

This European Standard was approved by CENELEC on 2009-04-01. CENELEC members are bound to comply
with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard
the status of a national standard without any alteration.

Up-to-date lists and bibliographical references concerning such national standards may be obtained on
application to the Central Secretariat or to any CENELEC member.

This European Standard exists in three official versions (English, French, German). A version in any other
language made by translation under the responsibility of a CENELEC member into its own language and notified
to the Central Secretariat has the same status as the official versions.

CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Cyprus, the
Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia,
Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain,
Sweden, Switzerland and the United Kingdom.

CENELEC
European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung

Central Secretariat: Avenue Marnix 17, B - 1000 Brussels

© 2009 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members.
Ref. No. EN 60424-5:2009 E
Foreword
The text of document 51/947/FDIS, future edition 1 of IEC 60424-5, prepared by IEC TC 51, Magnetic
components and ferrite materials, was submitted to the IEC-CENELEC parallel vote and was approved by
CENELEC as EN 60424-5 on 2009-04-01.
The following dates were fixed:
– latest date by which the EN has to be implemented
at national level by publication of an identical
national standard or by endorsement (dop) 2010-01-01
– latest date by which the national standards conflicting
with the EN have to be withdrawn (dow) 2012-04-01
Annex ZA has been added by CENELEC.
__________
Endorsement notice
The text of the International Standard IEC 60424-5:2009 was approved by CENELEC as a European
Standard without any modification.
__________
– 3 – EN 60424-5:2009
Annex ZA
(normative)
Normative references to international publications
with their corresponding European publications

The following referenced documents are indispensable for the application of this document. For dated
references, only the edition cited applies. For undated references, the latest edition of the referenced
document (including any amendments) applies.

NOTE  When an international publication has been modified by common modifications, indicated by (mod), the relevant EN/HD
applies.
Publication Year Title EN/HD Year

1) 2)
IEC 60424-1 - Ferrite cores - Guide on the limits of surface EN 60424-1 1999
irregularities -
Part 1: General specification
1) 2)
IEC 62317-9 - Ferrite cores - Dimensions - EN 62317-9 2006
Part 9: Planar cores
1)
Undated reference.
2)
Valid edition at date of issue.

IEC 60424-5 ®
Edition 1.0 2009-02
INTERNATIONAL
STANDARD
Ferrite cores – Guide on the limits of surface irregularities –
Part 5: Planar-cores
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
PRICE CODE
N
ICS 29.100.10 ISBN 2-8318-1032-6
– 2 – 60424-5 © IEC:2009(E)
CONTENTS
FOREWORD.3
1 Scope.5
2 Normative references .5
3 Limits of surface irregularities.6
3.1 Chips and ragged edges.6
3.1.1 Chips and ragged edges on the mating surfaces (see Figures 1, 2
and 3).6
3.1.2 Chips and ragged edges on other surfaces.7
3.2 Cracks.10
3.3 Flash.10
3.4 Pull-out .10

Figure 1 – Chip location for planar EL-core.6
Figure 2 – Chip location for low profile E-core.6
Figure 3 – Chip location for low profile ER-core .6
Figure 4 – Cracks and pull-out location for planar EL-core .10
Figure 5 – Cracks and pull-out location for low profile E-core.11
Figure 6 – Cracks and pull-out location for low profile ER-core .11
Figure 7 – Reference dimensions for EL-core .11
Figure 8 – Reference dimensions for E-core .12
Figure 9 – Reference dimensions for ER-core.13

Table 1 – Allowable areas of chips in mm for planar EL-core.7
Table 2 – Allowable areas of chips in mm for low profile E-core .8
Table 3 – Allowable areas of chips in mm for low profile ER-core .8
Table 4 – Area and length reference for visual inspection .9
Table 5 – Limits of cracks for planar EL-core .12
Table 6 – Limits of cracks for low profile E-core.13
Table 7 – Limits of cracks for low profile ER-core .14

60424-5 © IEC:2009(E) – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
FERRITE CORES –
GUIDE ON THE LIMITS OF SURFACE IRREGULARITIES –

Part 5: Planar-cores
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of the IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC
Publication(s)“). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and non-
governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely
with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
the latter.
5) IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with an IEC Publication.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60424-5 has been prepared by IEC technical committee 51:
Magnetic components and ferrite materials.
The text of this standard is based on the following documents:
FDIS Report on voting
51/947/FDIS 51/950/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts of the IEC 60424 series, under the general title Ferrite cores – Guide on the
limits of surface irregularities, can be found on the IEC website.

– 4 – 60424-5 © IEC:2009(E)
The committee has decided that the contents of this publication will remain unchanged until
the maintenance result date indicated on the IEC web site under "http://webstore.iec.ch" in
the data related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
A bilingual version of this publication may be issued at a later date.

60424-5 © IEC:2009(E) – 5 –
FERRITE CORES –
GUIDE ON THE LIMITS OF SURFACE IRREGULARITIES –

Part 5: Planar-cores
1 Scope
This part of IEC 60424 gives guidance on allowable limits of surface irregularities applicable
to planar-cores in accordance with the relevant generic specification defined in IEC 60424-1.
The relations between the main dimensions of planar E-, ER- and EL-cores differ from those
of standard cores. For example, the width of planar cores is larger while the total height is
much smaller. Also the thickness of the legs is in most cases smaller than compared to
standard cores. Therefore the concept of fixed reference dimensions to determine the length
of crack limits yield crack lengths which are not acceptable for this type of core. This part of
IEC 60424 follows another concept which relates the crack length to dimensions of the
surface on which the crack occurs.
Also the concept to determine the maximum area of chips based on the total mating surface
fails in the case of planar cores. The outer legs of planar cores are much thinner than those of
standard cores which makes overlapping and gluing much more difficult. A single chip of
maximum size on the outer leg may risk the functionality of the core set. Therefore this
standard uses as a reference the mating surface on which the chip occurs.
Windings of planar cores are often PCB’s which are glued to the inner surfaces of the planar
core. For this reason the inner surfaces of the planar cores need to have a better quality than
the inner surfaces of standard cores. This was taken into account by reducing the maximum
allowable area of pull outs in the inner surfaces.
This standard is considered as a sectional specification useful i
...

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