IEC 62528:2007

Standard Testability Method for Embedded Core-based Integrated Circuits

Defines a mechanism for the test of core designs within a system on chip (SoC).This mechanism constitutes a hardware architecture and leverages the core test language (CTL)to faciliate communication between core designers and core integrators.

General Information

• Status: Published
• Publication Date: 06-Nov-2007
• ICS: 01 - GENERALITIES. TERMINOLOGY. STANDARDIZATION. DOCUMENTATION
• ICS: 31.200 - Integrated circuits. Microelectronics
• Technical Committee: TC 91 - Electronics assembly technology
• Drafting Committee: WG 15 - TC 91/WG 15
• Current Stage: PPUB - Publication issued
• Start Date: 31-Oct-2007
• Completion Date: 07-Nov-2007

Standards Content (Sample)

IEC 62528
Edition 1.0 2007-11
™
IEEE 1500
INTERNATIONAL
STANDARD
Standard Testability Method for Embedded Core-based Integrated Circuits

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IEC 62528
Edition 1.0 2007-11
™
IEEE 1500
INTERNATIONAL
STANDARD
Standard testability method for embedded core-based integrated circuits

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
PRICE CODE
XF
ICS 31.220 ISBN 2-8318-9481-6
– 2 – IEC 62528:2007(E)
IEEE 1500-2005(E)
CONTENTS
FOREWORD . 4
IEE Introduction . 7
1. Overview.9
1.1 Scope.10
1.2 Purpose.10
2. Normative references.10
3. Definitions, acronyms, and abbreviations.11
3.1 Definitions .11
3.2 Acronyms and abbreviations .16
4. Structure of this standard .17
4.1 Specifications.17
4.2 Descriptions . 18
5. Introduction and motivations of two compliance levels. 18
6. Overview of the IEEE 1500 scalable hardware architecture . 19
6.1 Wrapper serial port (WSP) . 19
6.2 Wrapper parallel port (WPP) . 19
6.3 Wrapper instruction register (WIR).20
6.4 Wrapper bypass register (WBY).20
6.5 Wrapper boundary register (WBR).20
7. WIR instructions .21
7.1 Introduction.21
7.2 Response of the wrapper circuitry to instructions .13
7.3 Wrapper instruction rules and naming convention .23
7.4 WS_BYPASS Instruction .24
7.5 WS_EXTEST instruction .25
7.6 WP_EXTEST instruction .27
7.7 Wx_EXTEST instruction. 29
7.8 WS_SAFE instruction.30
7.9 WS_PRELOAD instruction.32
7.10 WP_PRELOAD instruction.32
7.11 WS_CLAMP instruction.34
7.12 WS_INTEST_RING instruction.36
7.13 WS_INTEST_SCAN instruction.37
7.14 Wx_INTEST instruction.40
8. Wrapper serial port (WSP) .41
8.1 WSP terminals .42
9. Wrapper parallel port (WPP) .43
9.1 WPP terminals .43
10. Wrapper instruction register (WIR).43
10.1 WIR configuration and DR selection.43
10.2 WIR design .44
10.3 WIR operation.47
11. Wrapper bypass register (WBY). 49
11.1 WBY register configuration and selection. 49
Published by IEC under licence from IEEE. © 2005 IEEE. All rights reserved.

IEEE 1500-2005(E)
11.2 WBY design. 50
11.3 WBY operation .51
12. Wrapper boundary register (WBR).52
12.1 WBR structure and operation .54
12.2 WBR cell structure and operation.55
12.3 WBR operation events .56
12.4 WBR operation modes. 59
12.5 Parallel access to the WBR.61
12.6 WBR cell naming.63
12.7 WBR cell examples .64
12.8 IEEE 1500 WBR example . 68
13. Wrapper states.71
13.1 Wrapper Disabled and Wrapper Enabled states .71
14. WSP timing diagram.72
14.1 Specifications.72
14.2 Description.73
14.3 Synchronous reset timing.77
15. WSP configurations for IEEE 1500 system chips . 78
15.1 Connecting multiple WSPs. 78
16. Plug-and-play (PnP).81
16.1 Background and definition.81
16.2 PnP aspects of standard instructions.82
16.3 PnP limitations on protocols .83
16.4 Non-PnP in IEEE Std 1500.83
17. Compliance definitions common to wrapped and unwrapped cores .83
17.1 General rules .83
17.2 Per-terminal rules.85
17.3 Test pattern information rules.86
18. Compliance definitions specific to unwrapped cores .89
18.1 General rules . 89
18.2 Per-terminal rules.90
18.3 Additional test information rules .90
19. Compliance definitions specific to wrapped cores .91
19.1 General rules .91
19.2 Per-terminal rules.92
19.3 Wrapper protocol information rules .92
20. IEEE 1500 application .93
20.1 CTL (IEEE P1450.6) overview .93
20.2 IEEE 1500 examples.
...