Digital Video Broadcasting (DVB) - Next Generation broadcasting system to Handheld, physical layer specification (DVB-NGH) - Part 1: Base Profile

The present document describes the next generation transmission system for digital terrestrial and hybrid (combination
of terrestrial with satellite transmissions) broadcasting to handheld terminals. It specifies the entire physical layer part
from the input streams to the transmitted signal. This transmission system is intended for carrying Transport Streams or
generic data streams feeding linear and non-linear applications like television, radio and data services. DVB-NGH
terminals might also process DVB-T2-lite signals.

Digitalna videoradiodifuzija (DVB) - Radiodifuzijski sistem naslednje generacije za dlančnike, specifikacija fizične plasti (DVB-NGH) - 1. del: Osnovni profil

Ta dokument opisuje sistem prenosa naslednje generacije za digitalno prizemno in hibridno (kombinacija prizemnih in satelitskih prenosov) radiodifuzijo, namenjeno ročno upravljanim terminalom. Določa celoten del fizične plasti od vhodnih tokov do prenesenega signala. Ta sistem prenosa je namenjen prenašanju transportnih tokov ali splošnih podatkovnih tokov v linearne in nelinearne aplikacije, kot so televizija, radio in podatkovne storitve. Terminali DVB-NGH lahko obdelujejo tudi signale DVB-T2-lite.

General Information

Status
Published
Public Enquiry End Date
31-Mar-2022
Publication Date
05-Apr-2022
Technical Committee
Current Stage
6060 - National Implementation/Publication (Adopted Project)
Start Date
04-Apr-2022
Due Date
09-Jun-2022
Completion Date
06-Apr-2022

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ETSI EN 303 105-1 V1.1.1 (2022-03)
EUROPEAN STANDARD
Digital Video Broadcasting (DVB);
Next Generation broadcasting system to Handheld,
physical layer specification (DVB-NGH);
Part 1: Base Profile
---------------------- Page: 1 ----------------------
2 ETSI EN 303 105-1 V1.1.1 (2022-03)
Reference
DEN/JTC-DVB-373-1
Keywords
audio, broadcasting, data, digital, DVB, hybrid,
MIMO, MPEG, radio, satellite, terrestrial, TV, video
ETSI
650 Route des Lucioles
F-06921 Sophia Antipolis Cedex - FRANCE
Tel.: +33 4 92 94 42 00 Fax: +33 4 93 65 47 16
Siret N° 348 623 562 00017 - APE 7112B
Association à but non lucratif enregistrée à la
Sous-Préfecture de Grasse (06) N° w061004871
Important notice
The present document can be downloaded from:
http://www.etsi.org/standards-search

The present document may be made available in electronic versions and/or in print. The content of any electronic and/or

print versions of the present document shall not be modified without the prior written authorization of ETSI. In case of any

existing or perceived difference in contents between such versions and/or in print, the prevailing version of an ETSI

deliverable is the one made publicly available in PDF format at www.etsi.org/deliver.

Users of the present document should be aware that the document may be subject to revision or change of status.

Information on the current status of this and other ETSI documents is available at

https://portal.etsi.org/TB/ETSIDeliverableStatus.aspx

If you find errors in the present document, please send your comment to one of the following services:

https://portal.etsi.org/People/CommiteeSupportStaff.aspx

If you find a security vulnerability in the present document, please report it through our

Coordinated Vulnerability Disclosure Program:
https://www.etsi.org/standards/coordinated-vulnerability-disclosure
Notice of disclaimer & limitation of liability

The information provided in the present deliverable is directed solely to professionals who have the appropriate degree of

experience to understand and interpret its content in accordance with generally accepted engineering or

other professional standard and applicable regulations.

No recommendation as to products and services or vendors is made or should be implied.

In no event shall ETSI be held liable for loss of profits or any other incidental or consequential damages.

Any software contained in this deliverable is provided "AS IS" with no warranties, express or implied, including but not

limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement of intellectual property

rights and ETSI shall not be held liable in any event for any damages whatsoever (including, without limitation, damages

for loss of profits, business interruption, loss of information, or any other pecuniary loss) arising out of or related to the use

of or inability to use the software.
Copyright Notification

No part may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying and

microfilm except as authorized by written permission of ETSI.

The content of the PDF version shall not be modified without the written authorization of ETSI.

The copyright and the foregoing restriction extend to reproduction in all media.
© ETSI 2022.
© European Broadcasting Union 2022.
All rights reserved.
ETSI
---------------------- Page: 2 ----------------------
3 ETSI EN 303 105-1 V1.1.1 (2022-03)
Contents

Intellectual Property Rights ................................................................................................................................ 9

Foreword ............................................................................................................................................................. 9

Modal verbs terminology .................................................................................................................................. 10

Introduction ...................................................................................................................................................... 10

1 Scope ...................................................................................................................................................... 11

2 References .............................................................................................................................................. 11

2.1 Normative references ....................................................................................................................................... 11

2.2 Informative references ...................................................................................................................................... 11

3 Definition of terms, symbols and abbreviations ..................................................................................... 12

3.1 Terms ................................................................................................................................................................ 12

3.2 Symbols ............................................................................................................................................................ 15

3.3 Abbreviations ................................................................................................................................................... 20

4 System overview and architecture .......................................................................................................... 22

4.1 Architecture ...................................................................................................................................................... 22

4.2 Input processing ............................................................................................................................................... 26

4.2.1 Architecture ................................................................................................................................................ 26

4.2.2 Mapping of input streams onto PLPs .......................................................................................................... 27

4.2.3 Encapsulation into baseband frames ........................................................................................................... 27

4.3 Bit-interleaved coding and modulation, MISO precoding ................................................................................ 27

4.3.1 Architecture ................................................................................................................................................ 27

4.3.2 FEC encoding and interleaving inside a FEC block ................................................................................... 27

4.3.3 Modulation and component interleaving .................................................................................................... 28

4.3.4 Formation of interleaving frames for each PLP .......................................................................................... 28

4.3.5 Time interleaving (inter-frame convolutional interleaving plus intra-frame block interleaving) ............... 28

4.4 Frame building, frequency interleaving ............................................................................................................ 28

4.4.1 Architecture ................................................................................................................................................ 28

4.4.2 Formation of logical frames ........................................................................................................................ 29

4.4.3 Mapping of logical frames onto NGH frames ............................................................................................ 29

4.4.4 Logical channel types ................................................................................................................................. 31

4.4.5 Single tuner reception for frequency hopping ............................................................................................. 31

4.5 OFDM generation............................................................................................................................................. 32

4.5.1 Architecture ................................................................................................................................................ 32

5 Input processing ..................................................................................................................................... 32

5.1 Mode adaptation ............................................................................................................................................... 32

5.1.1 Overview .................................................................................................................................................... 32

5.1.2 Input interface ............................................................................................................................................. 33

5.1.2.1 Overview ............................................................................................................................................... 33

5.1.2.2 Input formats, input formatting ............................................................................................................. 33

5.1.2.2.1 Overview ......................................................................................................................................... 33

5.1.2.2.2 Transport Stream packet header compression ................................................................................. 34

5.1.2.3 Subsequent processing of formatted input streams ............................................................................... 36

5.1.3 Input stream synchronization (optional) ..................................................................................................... 36

5.1.4 Compensating delay (optional) ................................................................................................................... 37

5.1.5 Null packet deletion (optional, for TS only, ISSY-IF, ISSY-BBF and ISSY-UP modes) .......................... 37

5.1.6 Baseband frame header (BBF-HDR) insertion ........................................................................................... 38

5.1.7 Mode adaptation sub-system output stream formats ................................................................................... 39

5.1.7.1 Overview ............................................................................................................................................... 39

5.1.7.2 ISSY-IF mode, TS (with or without packet header compression), GSE, GCS ..................................... 39

5.1.7.3 ISSY-BBF mode, TS (with or without packet header compression), GSE, GCS ................................. 40

5.1.7.4 ISSY-UP mode, TS (with or without packet header compression) and GSE ........................................ 41

5.2 Stream adaptation ............................................................................................................................................. 41

5.2.1 Overview .................................................................................................................................................... 41

5.2.2 Scheduler .................................................................................................................................................... 42

ETSI
---------------------- Page: 3 ----------------------
4 ETSI EN 303 105-1 V1.1.1 (2022-03)

5.2.3 Padding ....................................................................................................................................................... 42

5.2.4 Use of the padding field for in-band signalling .......................................................................................... 42

5.2.4.1 Overview ............................................................................................................................................... 42

5.2.4.2 In-band type A ...................................................................................................................................... 43

5.2.4.3 In-band type B ....................................................................................................................................... 46

5.2.5 Baseband frame scrambling ........................................................................................................................ 47

6 Bit-interleaved coding and modulation .................................................................................................. 48

6.1 FEC encoding ................................................................................................................................................... 48

6.1.1 Overview .................................................................................................................................................... 48

6.1.2 Outer encoding (BCH) ................................................................................................................................ 49

6.1.3 Inner encoding (LDPC) .............................................................................................................................. 50

6.1.4 Bit Interleaver ............................................................................................................................................. 51

6.2 Mapping bits onto constellations ...................................................................................................................... 52

6.2.1 Overview .................................................................................................................................................... 52

6.2.2 Bit to cellword de-multiplexer .................................................................................................................... 53

6.2.3 Cell word mapping into I/Q constellations ................................................................................................. 57

6.3 Cell interleaver ................................................................................................................................................. 59

6.4 Constellation rotation ....................................................................................................................................... 62

6.5 I/Q component interleaver ................................................................................................................................ 63

6.6 Time interleaver ............................................................................................................................................... 64

6.6.1 Overview .................................................................................................................................................... 64

6.6.2 Division of interleaving frames into time interleaving blocks .................................................................... 66

6.6.3 Writing of each TI-block into the time interleaver ..................................................................................... 67

6.6.4 Mapping of interleaving frames onto one or more logical frames .............................................................. 68

6.6.5 Number of cells available in the time interleaver ....................................................................................... 71

6.6.6 PLPs for which time interleaving is not used ............................................................................................. 72

7 Distributed and cross-polar MISO ......................................................................................................... 72

7.1 System overview .............................................................................................................................................. 72

7.2 Transmit/receive system compatibility ............................................................................................................. 72

7.3 MISO precoding ............................................................................................................................................... 72

7.4 eSFN processing for MISO .............................................................................................................................. 73

7.5 Power imbalance .............................................................................................................................................. 73

7.6 SISO/MISO options for P1, aP1 and P2 symbols............................................................................................. 73

8 Generation, coding and modulation of layer 1 signalling ...................................................................... 74

8.1 Introduction ...................................................................................................................................................... 74

8.2 L1 signalling data ............................................................................................................................................. 75

8.2.1 Overview .................................................................................................................................................... 75

8.2.2 P1 signalling data ........................................................................................................................................ 75

8.2.3 L1-PRE signalling data ............................................................................................................................... 77

8.2.3.1 Parameters ............................................................................................................................................. 77

8.2.3.2 N-periodic spreading of L1-PRE data ................................................................................................... 85

8.2.4 L1-POST signalling data ............................................................................................................................ 85

8.2.4.1 Overview ............................................................................................................................................... 85

8.2.4.2 L1-POST configurable signalling data .................................................................................................. 86

8.2.4.3 Self-decodable partitioning of the PLP loop in L1-POST configurable ................................................ 94

8.2.4.4 L1-POST dynamic signalling ................................................................................................................ 96

8.2.4.5 Repetition of L1-POST dynamic data ................................................................................................... 97

8.2.4.6 Additional parity of L1-POST dynamic data ........................................................................................ 98

8.2.4.7 L1-POST extension field ....................................................................................................................... 98

8.2.4.8 CRC for the L1-POST signalling .......................................................................................................... 99

8.2.4.9 L1 padding ............................................................................................................................................ 99

8.3 Modulation and error correction coding of the L1 data .................................................................................... 99

8.3.1 Overview .................................................................................................................................................... 99

8.3.1.1 Error correction coding and modulation of the L1-PRE signalling ....................................................... 99

8.3.1.2 Error correction coding and modulation of the L1-POST signalling .................................................. 100

8.3.2 Scrambling and FEC encoding ................................................................................................................. 103

8.3.2.1 Scrambling of L1-PRE and L1-POST information bits ...................................................................... 103

8.3.2.2 Zero padding of BCH information bits ............................................................................................... 103

8.3.2.3 BCH encoding ..................................................................................................................................... 105

8.3.2.4 LDPC encoding ................................................................................................................................... 105

ETSI
---------------------- Page: 4 ----------------------
5 ETSI EN 303 105-1 V1.1.1 (2022-03)

8.3.2.4.1 Introduction ................................................................................................................................... 105

8.3.2.4.2 LDPC encoding for L1-PRE .......................................................................................................... 106

8.3.2.4.3 LDPC encoding for L1-POST ....................................................................................................... 106

8.3.2.5 Puncturing of LDPC parity bits ........................................................................................................... 108

8.3.2.5.1 Puncturing of LDPC parity bits for L1-PRE ................................................................................. 108

8.3.2.5.2 Puncturing of LDPC parity bits for L1-POST ............................................................................... 110

8.3.2.6 Generation of additional parity for L1-POST signalling ..................................................................... 111

8.3.2.7 Removal of zero padding bits.............................................................................................................. 112

8.3.2.8 Bit interleaving for L1-POST signalling ............................................................................................. 112

8.3.3 Mapping bits onto constellations .............................................................................................................. 113

8.3.3.1 Overview ............................................................................................................................................. 113

8.3.3.2 Mapping of L1-PRE signalling ........................................................................................................... 113

8.3.3.3 Demultiplexing of L1-POST signalling .............................................................................................. 114

8.3.3.4 Mapping into I/Q constellations .......................................................................................................... 115

9 Frames .................................................................................................................................................. 115

9.1 Frame builder ................................................................................................................................................. 115

9.2 Logical frame structure .................................................................................................................................. 116

9.2.1 Overview .................................................................................................................................................. 116

9.2.2 Signalling of the logical frame .................................................................................................................. 117

9.2.3 Mapping the PLPs onto logical frames ..................................................................................................... 117

9.2.3.1 Overview ............................................................................................................................................. 117

9.2.3.2 Allocating the cells at the output of the time interleaver for a given PLP ........................................... 117

9.2.3.3 Allocating the cells of the PLPs .......................................................................................................... 118

9.2.3.3.1 Overview ....................................................................................................................................... 118

9.2.3.3.2 Allocating the cells of the common and type 1 PLPs .................................................................... 118

9.2.3.3.3 Allocating the cells of type 2 PLPs................................................................................................ 119

9.2.3.3.4 Allocation of cells positions in the logical frame for each of the type 2 PLPs .............................. 119

9.2.3.3.5 Mapping of the time interleaver output cells for each type 2 PLP, together with any padding,

to the allocated cell positions in the logical frame ......................................................................... 122

9.2.3.3.6 Allocating the cells of type 3 PLPs................................................................................................ 123

9.2.3.3.7 Allocating the cells of type 4 PLPs................................................................................................ 123

9.2.4 Auxiliary stream insertion ........................................................................................................................ 124

9.2.5 Dummy cell insertion................................................................................................................................ 124

9.3 Logical super-frame structure ......................................................................................................................... 124

9.4 Logical channel structure ............................................................................................................................... 125

9.4.1 Overview .................................................................................................................................................. 125

9.4.2 Logical channel type A ............................................................................................................................. 125

9.4.3 Logical channel type B ............................................................................................................................. 126

9.4.4 Logical channel type C ............................................................................................................................. 126

9.4.5 Logical channel type D ............................................................................................................................. 126

9.4.6 Logical channel group .............................................................................................................................. 127

9.5 Mapping of logical channels to NGH frames ................................................................................................. 127

9.5.1 Overview .................................................................................................................................................. 127

9.5.2 Mapping for logical channels type A ........................................................................................................ 127

9.5.3 Mapping for logical channels type B ........................................................................................................ 128

9.5.4 Mapping for logical channels type C ........................................................................................................ 128

9.5.5 Mapping for logical channels type D ........................................................................................................ 128

9.5.6 Restrictions on frame structure to allow tuner switching time for logical channels of types C and D ..... 128

9.6 NGH frame structure ...................................................................................................................................... 129

9.7 Super-frame .................................................................................................................................................... 130

9.8 NGH frame ..................................................................................................................................................... 131

9.8.1 Overview .................................................................................................................................................. 131

9.8.2 Duration of the NGH frame ...................................................................................................................... 131

9.8.3 Capacity and structure of the NGH frame ................................................................................................ 132

9.8.4 Mapping of L1-PRE signalling information to P2 symbol(s) ................................................................... 134

9.8.4.1 Introduction ......................................................................................................................................... 134

9.8.4.2 Addressing of OFDM cells ............................................................................................

...

SLOVENSKI STANDARD
SIST EN 303 105-1 V1.1.1:2022
01-maj-2022

Digitalna videoradiodifuzija (DVB) - Radiodifuzijski sistem naslednje generacije za

dlančnike, specifikacija fizične plasti (DVB-NGH) - 1. del: Osnovni profil

Digital Video Broadcasting (DVB) - Next Generation broadcasting system to Handheld,

physical layer specification (DVB-NGH) - Part 1: Base Profile
Ta slovenski standard je istoveten z: ETSI EN 303 105-1 V1.1.1 (2022-03)
ICS:
33.170 Televizijska in radijska Television and radio
difuzija broadcasting
35.100.10 Fizični sloj Physical layer
SIST EN 303 105-1 V1.1.1:2022 en

2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

---------------------- Page: 1 ----------------------
SIST EN 303 105-1 V1.1.1:2022
---------------------- Page: 2 ----------------------
SIST EN 303 105-1 V1.1.1:2022
ETSI EN 303 105-1 V1.1.1 (2022-03)
EUROPEAN STANDARD
Digital Video Broadcasting (DVB);
Next Generation broadcasting system to Handheld,
physical layer specification (DVB-NGH);
Part 1: Base Profile
---------------------- Page: 3 ----------------------
SIST EN 303 105-1 V1.1.1:2022
2 ETSI EN 303 105-1 V1.1.1 (2022-03)
Reference
DEN/JTC-DVB-373-1
Keywords
audio, broadcasting, data, digital, DVB, hybrid,
MIMO, MPEG, radio, satellite, terrestrial, TV, video
ETSI
650 Route des Lucioles
F-06921 Sophia Antipolis Cedex - FRANCE
Tel.: +33 4 92 94 42 00 Fax: +33 4 93 65 47 16
Siret N° 348 623 562 00017 - APE 7112B
Association à but non lucratif enregistrée à la
Sous-Préfecture de Grasse (06) N° w061004871
Important notice
The present document can be downloaded from:
http://www.etsi.org/standards-search

The present document may be made available in electronic versions and/or in print. The content of any electronic and/or

print versions of the present document shall not be modified without the prior written authorization of ETSI. In case of any

existing or perceived difference in contents between such versions and/or in print, the prevailing version of an ETSI

deliverable is the one made publicly available in PDF format at www.etsi.org/deliver.

Users of the present document should be aware that the document may be subject to revision or change of status.

Information on the current status of this and other ETSI documents is available at

https://portal.etsi.org/TB/ETSIDeliverableStatus.aspx

If you find errors in the present document, please send your comment to one of the following services:

https://portal.etsi.org/People/CommiteeSupportStaff.aspx

If you find a security vulnerability in the present document, please report it through our

Coordinated Vulnerability Disclosure Program:
https://www.etsi.org/standards/coordinated-vulnerability-disclosure
Notice of disclaimer & limitation of liability

The information provided in the present deliverable is directed solely to professionals who have the appropriate degree of

experience to understand and interpret its content in accordance with generally accepted engineering or

other professional standard and applicable regulations.

No recommendation as to products and services or vendors is made or should be implied.

In no event shall ETSI be held liable for loss of profits or any other incidental or consequential damages.

Any software contained in this deliverable is provided "AS IS" with no warranties, express or implied, including but not

limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement of intellectual property

rights and ETSI shall not be held liable in any event for any damages whatsoever (including, without limitation, damages

for loss of profits, business interruption, loss of information, or any other pecuniary loss) arising out of or related to the use

of or inability to use the software.
Copyright Notification

No part may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying and

microfilm except as authorized by written permission of ETSI.

The content of the PDF version shall not be modified without the written authorization of ETSI.

The copyright and the foregoing restriction extend to reproduction in all media.
© ETSI 2022.
© European Broadcasting Union 2022.
All rights reserved.
ETSI
---------------------- Page: 4 ----------------------
SIST EN 303 105-1 V1.1.1:2022
3 ETSI EN 303 105-1 V1.1.1 (2022-03)
Contents

Intellectual Property Rights ................................................................................................................................ 9

Foreword ............................................................................................................................................................. 9

Modal verbs terminology .................................................................................................................................. 10

Introduction ...................................................................................................................................................... 10

1 Scope ...................................................................................................................................................... 11

2 References .............................................................................................................................................. 11

2.1 Normative references ....................................................................................................................................... 11

2.2 Informative references ...................................................................................................................................... 11

3 Definition of terms, symbols and abbreviations ..................................................................................... 12

3.1 Terms ................................................................................................................................................................ 12

3.2 Symbols ............................................................................................................................................................ 15

3.3 Abbreviations ................................................................................................................................................... 20

4 System overview and architecture .......................................................................................................... 22

4.1 Architecture ...................................................................................................................................................... 22

4.2 Input processing ............................................................................................................................................... 26

4.2.1 Architecture ................................................................................................................................................ 26

4.2.2 Mapping of input streams onto PLPs .......................................................................................................... 27

4.2.3 Encapsulation into baseband frames ........................................................................................................... 27

4.3 Bit-interleaved coding and modulation, MISO precoding ................................................................................ 27

4.3.1 Architecture ................................................................................................................................................ 27

4.3.2 FEC encoding and interleaving inside a FEC block ................................................................................... 27

4.3.3 Modulation and component interleaving .................................................................................................... 28

4.3.4 Formation of interleaving frames for each PLP .......................................................................................... 28

4.3.5 Time interleaving (inter-frame convolutional interleaving plus intra-frame block interleaving) ............... 28

4.4 Frame building, frequency interleaving ............................................................................................................ 28

4.4.1 Architecture ................................................................................................................................................ 28

4.4.2 Formation of logical frames ........................................................................................................................ 29

4.4.3 Mapping of logical frames onto NGH frames ............................................................................................ 29

4.4.4 Logical channel types ................................................................................................................................. 31

4.4.5 Single tuner reception for frequency hopping ............................................................................................. 31

4.5 OFDM generation............................................................................................................................................. 32

4.5.1 Architecture ................................................................................................................................................ 32

5 Input processing ..................................................................................................................................... 32

5.1 Mode adaptation ............................................................................................................................................... 32

5.1.1 Overview .................................................................................................................................................... 32

5.1.2 Input interface ............................................................................................................................................. 33

5.1.2.1 Overview ............................................................................................................................................... 33

5.1.2.2 Input formats, input formatting ............................................................................................................. 33

5.1.2.2.1 Overview ......................................................................................................................................... 33

5.1.2.2.2 Transport Stream packet header compression ................................................................................. 34

5.1.2.3 Subsequent processing of formatted input streams ............................................................................... 36

5.1.3 Input stream synchronization (optional) ..................................................................................................... 36

5.1.4 Compensating delay (optional) ................................................................................................................... 37

5.1.5 Null packet deletion (optional, for TS only, ISSY-IF, ISSY-BBF and ISSY-UP modes) .......................... 37

5.1.6 Baseband frame header (BBF-HDR) insertion ........................................................................................... 38

5.1.7 Mode adaptation sub-system output stream formats ................................................................................... 39

5.1.7.1 Overview ............................................................................................................................................... 39

5.1.7.2 ISSY-IF mode, TS (with or without packet header compression), GSE, GCS ..................................... 39

5.1.7.3 ISSY-BBF mode, TS (with or without packet header compression), GSE, GCS ................................. 40

5.1.7.4 ISSY-UP mode, TS (with or without packet header compression) and GSE ........................................ 41

5.2 Stream adaptation ............................................................................................................................................. 41

5.2.1 Overview .................................................................................................................................................... 41

5.2.2 Scheduler .................................................................................................................................................... 42

ETSI
---------------------- Page: 5 ----------------------
SIST EN 303 105-1 V1.1.1:2022
4 ETSI EN 303 105-1 V1.1.1 (2022-03)

5.2.3 Padding ....................................................................................................................................................... 42

5.2.4 Use of the padding field for in-band signalling .......................................................................................... 42

5.2.4.1 Overview ............................................................................................................................................... 42

5.2.4.2 In-band type A ...................................................................................................................................... 43

5.2.4.3 In-band type B ....................................................................................................................................... 46

5.2.5 Baseband frame scrambling ........................................................................................................................ 47

6 Bit-interleaved coding and modulation .................................................................................................. 48

6.1 FEC encoding ................................................................................................................................................... 48

6.1.1 Overview .................................................................................................................................................... 48

6.1.2 Outer encoding (BCH) ................................................................................................................................ 49

6.1.3 Inner encoding (LDPC) .............................................................................................................................. 50

6.1.4 Bit Interleaver ............................................................................................................................................. 51

6.2 Mapping bits onto constellations ...................................................................................................................... 52

6.2.1 Overview .................................................................................................................................................... 52

6.2.2 Bit to cellword de-multiplexer .................................................................................................................... 53

6.2.3 Cell word mapping into I/Q constellations ................................................................................................. 57

6.3 Cell interleaver ................................................................................................................................................. 59

6.4 Constellation rotation ....................................................................................................................................... 62

6.5 I/Q component interleaver ................................................................................................................................ 63

6.6 Time interleaver ............................................................................................................................................... 64

6.6.1 Overview .................................................................................................................................................... 64

6.6.2 Division of interleaving frames into time interleaving blocks .................................................................... 66

6.6.3 Writing of each TI-block into the time interleaver ..................................................................................... 67

6.6.4 Mapping of interleaving frames onto one or more logical frames .............................................................. 68

6.6.5 Number of cells available in the time interleaver ....................................................................................... 71

6.6.6 PLPs for which time interleaving is not used ............................................................................................. 72

7 Distributed and cross-polar MISO ......................................................................................................... 72

7.1 System overview .............................................................................................................................................. 72

7.2 Transmit/receive system compatibility ............................................................................................................. 72

7.3 MISO precoding ............................................................................................................................................... 72

7.4 eSFN processing for MISO .............................................................................................................................. 73

7.5 Power imbalance .............................................................................................................................................. 73

7.6 SISO/MISO options for P1, aP1 and P2 symbols............................................................................................. 73

8 Generation, coding and modulation of layer 1 signalling ...................................................................... 74

8.1 Introduction ...................................................................................................................................................... 74

8.2 L1 signalling data ............................................................................................................................................. 75

8.2.1 Overview .................................................................................................................................................... 75

8.2.2 P1 signalling data ........................................................................................................................................ 75

8.2.3 L1-PRE signalling data ............................................................................................................................... 77

8.2.3.1 Parameters ............................................................................................................................................. 77

8.2.3.2 N-periodic spreading of L1-PRE data ................................................................................................... 85

8.2.4 L1-POST signalling data ............................................................................................................................ 85

8.2.4.1 Overview ............................................................................................................................................... 85

8.2.4.2 L1-POST configurable signalling data .................................................................................................. 86

8.2.4.3 Self-decodable partitioning of the PLP loop in L1-POST configurable ................................................ 94

8.2.4.4 L1-POST dynamic signalling ................................................................................................................ 96

8.2.4.5 Repetition of L1-POST dynamic data ................................................................................................... 97

8.2.4.6 Additional parity of L1-POST dynamic data ........................................................................................ 98

8.2.4.7 L1-POST extension field ....................................................................................................................... 98

8.2.4.8 CRC for the L1-POST signalling .......................................................................................................... 99

8.2.4.9 L1 padding ............................................................................................................................................ 99

8.3 Modulation and error correction coding of the L1 data .................................................................................... 99

8.3.1 Overview .................................................................................................................................................... 99

8.3.1.1 Error correction coding and modulation of the L1-PRE signalling ....................................................... 99

8.3.1.2 Error correction coding and modulation of the L1-POST signalling .................................................. 100

8.3.2 Scrambling and FEC encoding ................................................................................................................. 103

8.3.2.1 Scrambling of L1-PRE and L1-POST information bits ...................................................................... 103

8.3.2.2 Zero padding of BCH information bits ............................................................................................... 103

8.3.2.3 BCH encoding ..................................................................................................................................... 105

8.3.2.4 LDPC encoding ................................................................................................................................... 105

ETSI
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SIST EN 303 105-1 V1.1.1:2022
5 ETSI EN 303 105-1 V1.1.1 (2022-03)

8.3.2.4.1 Introduction ................................................................................................................................... 105

8.3.2.4.2 LDPC encoding for L1-PRE .......................................................................................................... 106

8.3.2.4.3 LDPC encoding for L1-POST ....................................................................................................... 106

8.3.2.5 Puncturing of LDPC parity bits ........................................................................................................... 108

8.3.2.5.1 Puncturing of LDPC parity bits for L1-PRE ................................................................................. 108

8.3.2.5.2 Puncturing of LDPC parity bits for L1-POST ............................................................................... 110

8.3.2.6 Generation of additional parity for L1-POST signalling ..................................................................... 111

8.3.2.7 Removal of zero padding bits.............................................................................................................. 112

8.3.2.8 Bit interleaving for L1-POST signalling ............................................................................................. 112

8.3.3 Mapping bits onto constellations .............................................................................................................. 113

8.3.3.1 Overview ............................................................................................................................................. 113

8.3.3.2 Mapping of L1-PRE signalling ........................................................................................................... 113

8.3.3.3 Demultiplexing of L1-POST signalling .............................................................................................. 114

8.3.3.4 Mapping into I/Q constellations .......................................................................................................... 115

9 Frames .................................................................................................................................................. 115

9.1 Frame builder ................................................................................................................................................. 115

9.2 Logical frame structure .................................................................................................................................. 116

9.2.1 Overview .................................................................................................................................................. 116

9.2.2 Signalling of the logical frame .................................................................................................................. 117

9.2.3 Mapping the PLPs onto logical frames ..................................................................................................... 117

9.2.3.1 Overview ............................................................................................................................................. 117

9.2.3.2 Allocating the cells at the output of the time interleaver for a given PLP ........................................... 117

9.2.3.3 Allocating the cells of the PLPs .......................................................................................................... 118

9.2.3.3.1 Overview ....................................................................................................................................... 118

9.2.3.3.2 Allocating the cells of the common and type 1 PLPs .................................................................... 118

9.2.3.3.3 Allocating the cells of type 2 PLPs................................................................................................ 119

9.2.3.3.4 Allocation of cells positions in the logical frame for each of the type 2 PLPs .............................. 119

9.2.3.3.5 Mapping of the time interleaver output cells for each type 2 PLP, together with any padding,

to the allocated cell positions in the logical frame ......................................................................... 122

9.2.3.3.6 Allocating the cells of type 3 PLPs................................................................................................ 123

9.2.3.3.7 Allocating the cells of type 4 PLPs................................................................................................ 123

9.2.4 Auxiliary stream insertion ........................................................................................................................ 124

9.2.5 Dummy cell insertion................................................................................................................................ 124

9.3 Logical super-frame structure ......................................................................................................................... 124

9.4 Logical channel structure ............................................................................................................................... 125

9.4.1 Overview .................................................................................................................................................. 125

9.4.2 Logical channel type A ............................................................................................................................. 125

9.4.3 Logical channel type B ............................................................................................................................. 126

9.4.4 Logical channel type C ............................................................................................................................. 126

9.4.5 Logical channel type D ............................................................................................................................. 126

9.4.6 Logical channel group .............................................................................................................................. 127

9.5 Mapping of logical channels to NGH frames ................................................................................................. 127

9.5.1 Overview .................................................................................................................................................. 127

9.5.2 Mapping for logical channels type A ........................................................................................................ 127

9.5.3 Mapping for logical channels type B ........................................................................................................ 128

9.5.4 Mapping for logical channels type C ........................................................................................................ 128

9.5.5 Mapping for logical channels type D ........................................................................................................ 128

9.5.6 Restrictions on frame structure to allow tuner switching time for logical channels of types C and D ..... 128

9.6 NGH frame structure ...................................................................................................................................... 129

9.7 Super-frame .................................................................................................................................................... 130

9.8 NGH frame .............................................
...

SLOVENSKI STANDARD
oSIST prEN 303 105-1 V1.0.3:2022
01-april-2022

Digitalna videoradiodifuzija (DVB) - Radiodifuzijski sistem naslednje generacije za

dlančnike, specifikacija fizične plasti (DVB-NGH) - 1. del: Osnovni profil

Digital Video Broadcasting (DVB) - Next Generation broadcasting system to Handheld,

physical layer specification (DVB-NGH) - Part 1: Base Profile
Ta slovenski standard je istoveten z: ETSI EN 303 105-1 V1.0.3 (2021-12)
ICS:
33.170 Televizijska in radijska Television and radio
difuzija broadcasting
35.100.10 Fizični sloj Physical layer
oSIST prEN 303 105-1 V1.0.3:2022 en

2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

---------------------- Page: 1 ----------------------
oSIST prEN 303 105-1 V1.0.3:2022
---------------------- Page: 2 ----------------------
oSIST prEN 303 105-1 V1.0.3:2022
Draft ETSI EN 303 105-1 V1.0.3 (2021-12)
EUROPEAN STANDARD
Digital Video Broadcasting (DVB);
Next Generation broadcasting system to Handheld,
physical layer specification (DVB-NGH);
Part 1: Base Profile
---------------------- Page: 3 ----------------------
oSIST prEN 303 105-1 V1.0.3:2022
2 Draft ETSI EN 303 105-1 V1.0.3 (2021-12)
Reference
DEN/JTC-DVB-373-1
Keywords
audio, broadcasting, data, digital, DVB, hybrid,
MIMO, MPEG, radio, satellite, terrestrial, TV, video
ETSI
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ETSI
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oSIST prEN 303 105-1 V1.0.3:2022
3 Draft ETSI EN 303 105-1 V1.0.3 (2021-12)
Contents

Intellectual Property Rights ................................................................................................................................ 9

Foreword ............................................................................................................................................................. 9

Modal verbs terminology .................................................................................................................................. 10

Introduction ...................................................................................................................................................... 10

1 Scope ...................................................................................................................................................... 11

2 References .............................................................................................................................................. 11

2.1 Normative references ....................................................................................................................................... 11

2.2 Informative references ...................................................................................................................................... 11

3 Definition of terms, symbols and abbreviations ..................................................................................... 12

3.1 Terms ................................................................................................................................................................ 12

3.2 Symbols ............................................................................................................................................................ 15

3.3 Abbreviations ................................................................................................................................................... 20

4 System overview and architecture .......................................................................................................... 22

4.1 Architecture ...................................................................................................................................................... 22

4.2 Input processing ............................................................................................................................................... 26

4.2.1 Architecture ................................................................................................................................................ 26

4.2.2 Mapping of input streams onto PLPs .......................................................................................................... 27

4.2.3 Encapsulation into baseband frames ........................................................................................................... 27

4.3 Bit-interleaved coding and modulation, MISO precoding ................................................................................ 27

4.3.1 Architecture ................................................................................................................................................ 27

4.3.2 FEC encoding and interleaving inside a FEC block ................................................................................... 27

4.3.3 Modulation and component interleaving .................................................................................................... 28

4.3.4 Formation of interleaving frames for each PLP .......................................................................................... 28

4.3.5 Time interleaving (inter-frame convolutional interleaving plus intra-frame block interleaving) ............... 28

4.4 Frame building, frequency interleaving ............................................................................................................ 28

4.4.1 Architecture ................................................................................................................................................ 28

4.4.2 Formation of logical frames ........................................................................................................................ 29

4.4.3 Mapping of logical frames onto NGH frames ............................................................................................ 29

4.4.4 Logical channel types ................................................................................................................................. 31

4.4.5 Single tuner reception for frequency hopping ............................................................................................. 31

4.5 OFDM generation............................................................................................................................................. 32

4.5.1 Architecture ................................................................................................................................................ 32

5 Input processing ..................................................................................................................................... 32

5.1 Mode adaptation ............................................................................................................................................... 32

5.1.1 Overview .................................................................................................................................................... 32

5.1.2 Input interface ............................................................................................................................................. 33

5.1.2.1 Overview ............................................................................................................................................... 33

5.1.2.2 Input formats, input formatting ............................................................................................................. 33

5.1.2.2.1 Overview ......................................................................................................................................... 33

5.1.2.2.2 Transport Stream packet header compression ................................................................................. 34

5.1.2.3 Subsequent processing of formatted input streams ............................................................................... 36

5.1.3 Input stream synchronization (optional) ..................................................................................................... 36

5.1.4 Compensating delay (optional) ................................................................................................................... 37

5.1.5 Null packet deletion (optional, for TS only, ISSY-IF, ISSY-BBF and ISSY-UP modes) .......................... 37

5.1.6 Baseband frame header (BBF-HDR) insertion ........................................................................................... 38

5.1.7 Mode adaptation sub-system output stream formats ................................................................................... 39

5.1.7.1 Overview ............................................................................................................................................... 39

5.1.7.2 ISSY-IF mode, TS (with or without packet header compression), GSE, GCS ..................................... 39

5.1.7.3 ISSY-BBF mode, TS (with or without packet header compression), GSE, GCS ................................. 40

5.1.7.4 ISSY-UP mode, TS (with or without packet header compression) and GSE ........................................ 41

5.2 Stream adaptation ............................................................................................................................................. 41

5.2.1 Overview .................................................................................................................................................... 41

5.2.2 Scheduler .................................................................................................................................................... 42

ETSI
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oSIST prEN 303 105-1 V1.0.3:2022
4 Draft ETSI EN 303 105-1 V1.0.3 (2021-12)

5.2.3 Padding ....................................................................................................................................................... 42

5.2.4 Use of the padding field for in-band signalling .......................................................................................... 42

5.2.4.1 Overview ............................................................................................................................................... 42

5.2.4.2 In-band type A ...................................................................................................................................... 43

5.2.4.3 In-band type B ....................................................................................................................................... 46

5.2.5 Baseband frame scrambling ........................................................................................................................ 47

6 Bit-interleaved coding and modulation .................................................................................................. 48

6.1 FEC encoding ................................................................................................................................................... 48

6.1.1 Overview .................................................................................................................................................... 48

6.1.2 Outer encoding (BCH) ................................................................................................................................ 49

6.1.3 Inner encoding (LDPC) .............................................................................................................................. 50

6.1.4 Bit Interleaver ............................................................................................................................................. 51

6.2 Mapping bits onto constellations ...................................................................................................................... 52

6.2.1 Overview .................................................................................................................................................... 52

6.2.2 Bit to cellword de-multiplexer .................................................................................................................... 53

6.2.3 Cell word mapping into I/Q constellations ................................................................................................. 57

6.3 Cell interleaver ................................................................................................................................................. 59

6.4 Constellation rotation ....................................................................................................................................... 62

6.5 I/Q component interleaver ................................................................................................................................ 63

6.6 Time interleaver ............................................................................................................................................... 64

6.6.1 Overview .................................................................................................................................................... 64

6.6.2 Division of interleaving frames into time interleaving blocks .................................................................... 66

6.6.3 Writing of each TI-block into the time interleaver ..................................................................................... 67

6.6.4 Mapping of interleaving frames onto one or more logical frames .............................................................. 68

6.6.5 Number of cells available in the time interleaver ....................................................................................... 71

6.6.6 PLPs for which time interleaving is not used ............................................................................................. 72

7 Distributed and cross-polar MISO ......................................................................................................... 72

7.1 System overview .............................................................................................................................................. 72

7.2 Transmit/receive system compatibility ............................................................................................................. 72

7.3 MISO precoding ............................................................................................................................................... 72

7.4 eSFN processing for MISO .............................................................................................................................. 73

7.5 Power imbalance .............................................................................................................................................. 73

7.6 SISO/MISO options for P1, aP1 and P2 symbols............................................................................................. 73

8 Generation, coding and modulation of layer 1 signalling ...................................................................... 74

8.1 Introduction ...................................................................................................................................................... 74

8.2 L1 signalling data ............................................................................................................................................. 75

8.2.1 Overview .................................................................................................................................................... 75

8.2.2 P1 signalling data ........................................................................................................................................ 75

8.2.3 L1-PRE signalling data ............................................................................................................................... 77

8.2.3.1 Parameters ............................................................................................................................................. 77

8.2.3.2 N-periodic spreading of L1-PRE data ................................................................................................... 85

8.2.4 L1-POST signalling data ............................................................................................................................ 85

8.2.4.1 Overview ............................................................................................................................................... 85

8.2.4.2 L1-POST configurable signalling data .................................................................................................. 86

8.2.4.3 Self-decodable partitioning of the PLP loop in L1-POST configurable ................................................ 94

8.2.4.4 L1-POST dynamic signalling ................................................................................................................ 96

8.2.4.5 Repetition of L1-POST dynamic data ................................................................................................... 97

8.2.4.6 Additional parity of L1-POST dynamic data ........................................................................................ 98

8.2.4.7 L1-POST extension field ....................................................................................................................... 98

8.2.4.8 CRC for the L1-POST signalling .......................................................................................................... 99

8.2.4.9 L1 padding ............................................................................................................................................ 99

8.3 Modulation and error correction coding of the L1 data .................................................................................... 99

8.3.1 Overview .................................................................................................................................................... 99

8.3.1.1 Error correction coding and modulation of the L1-PRE signalling ....................................................... 99

8.3.1.2 Error correction coding and modulation of the L1-POST signalling .................................................. 100

8.3.2 Scrambling and FEC encoding ................................................................................................................. 103

8.3.2.1 Scrambling of L1-PRE and L1-POST information bits ...................................................................... 103

8.3.2.2 Zero padding of BCH information bits ............................................................................................... 103

8.3.2.3 BCH encoding ..................................................................................................................................... 105

8.3.2.4 LDPC encoding ................................................................................................................................... 105

ETSI
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oSIST prEN 303 105-1 V1.0.3:2022
5 Draft ETSI EN 303 105-1 V1.0.3 (2021-12)

8.3.2.4.1 Introduction ................................................................................................................................... 105

8.3.2.4.2 LDPC encoding for L1-PRE .......................................................................................................... 106

8.3.2.4.3 LDPC encoding for L1-POST ....................................................................................................... 106

8.3.2.5 Puncturing of LDPC parity bits ........................................................................................................... 108

8.3.2.5.1 Puncturing of LDPC parity bits for L1-PRE ................................................................................. 108

8.3.2.5.2 Puncturing of LDPC parity bits for L1-POST ............................................................................... 110

8.3.2.6 Generation of additional parity for L1-POST signalling ..................................................................... 111

8.3.2.7 Removal of zero padding bits.............................................................................................................. 112

8.3.2.8 Bit interleaving for L1-POST signalling ............................................................................................. 112

8.3.3 Mapping bits onto constellations .............................................................................................................. 113

8.3.3.1 Overview ............................................................................................................................................. 113

8.3.3.2 Mapping of L1-PRE signalling ........................................................................................................... 113

8.3.3.3 Demultiplexing of L1-POST signalling .............................................................................................. 114

8.3.3.4 Mapping into I/Q constellations .......................................................................................................... 115

9 Frames .................................................................................................................................................. 115

9.1 Frame builder ................................................................................................................................................. 115

9.2 Logical frame structure .................................................................................................................................. 116

9.2.1 Overview .................................................................................................................................................. 116

9.2.2 Signalling of the logical frame .................................................................................................................. 117

9.2.3 Mapping the PLPs onto logical frames ..................................................................................................... 117

9.2.3.1 Overview ............................................................................................................................................. 117

9.2.3.2 Allocating the cells at the output of the time interleaver for a given PLP ........................................... 117

9.2.3.3 Allocating the cells of the PLPs .......................................................................................................... 118

9.2.3.3.1 Overview ....................................................................................................................................... 118

9.2.3.3.2 Allocating the cells of the common and type 1 PLPs .................................................................... 118

9.2.3.3.3 Allocating the cells of type 2 PLPs................................................................................................ 119

9.2.3.3.4 Allocation of cells positions in the logical frame for each of the type 2 PLPs .............................. 119

9.2.3.3.5 Mapping of the time interleaver output cells for each type 2 PLP, together with any padding,

to the allocated cell positions in the logical frame ......................................................................... 122

9.2.3.3.6 Allocating the cells of type 3 PLPs................................................................................................ 123

9.2.3.3.7 Allocating the cells of type 4 PLPs................................................................................................ 123

9.2.4 Auxiliary stream insertion ........................................................................................................................ 124

9.2.5 Dummy cell insertion................................................................................................................................ 124

9.3 Logical super-frame structure ......................................................................................................................... 124

9.4 Logical channel structure ............................................................................................................................... 125

9.4.1 Overview .................................................................................................................................................. 125

9.4.2 Logical channel type A ............................................................................................................................. 125

9.4.3 Logical channel type B ............................................................................................................................. 126

9.4.4 Logical channel type C ............................................................................................................................. 126

9.4.5 Logical channel type D ............................................................................................................................. 126

9.4.6 Logical channel group .............................................................................................................................. 127

9.5 Mapping of logical channels to NGH frames ................................................................................................. 127

9.5.1 Overview .................................................................................................................................................. 127

9.5.2 Mapping for logical channels type A ........................................................................................................ 127

9.5.3 Mapping for logical channels type B ........................................................................................................ 128

9.5.4 Mapping for logical channels type C ........................................................................................................ 128

9.5.5 Mapping for logical channels type D ........................................................................................................ 128

9.5.6 Restrictions on frame structure to allow tuner switching time for logical channels of types C and D ..... 128

9.6 NGH frame structure ...................................................................................................................................... 129

9.7 Super-frame .................................................................................................................................................... 130

9.8 NGH frame ..................................................................................................................................................... 131

9.8.1 Overview ................................
...

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