IEC PAS 62326-20:2011
(Main)Printed boards - Part 20: Electronic circuit board for high-brightness LEDs
Printed boards - Part 20: Electronic circuit board for high-brightness LEDs
IEC/PAS 62326-20:2011(E) specifies the properties of the electronic circuit board for high-brightness LEDs (hereafter described as "ECB").
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IEC/PAS 62326-20
®
Edition 1.0 2011-01
PUBLICLY AVAILABLE
SPECIFICATION
PRE-STANDARD
colour
inside
Printed boards –
Part 20: Electronic circuit board for high-brightness LEDs
IEC/PAS 62326-20:2011(E)
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IEC/PAS 62326-20
®
Edition 1.0 2011-01
PUBLICLY AVAILABLE
SPECIFICATION
PRE-STANDARD
colour
inside
Printed boards –
Part 20: Electronic circuit board for high-brightness LEDs
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
PRICE CODE
X
ICS 31.180 ISBN 978-2-88912-345-2
® Registered trademark of the International Electrotechnical Commission
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– 2 – PAS 62326-20 IEC:2011(E)
CONTENTS
FOREWORD . 6
1 Scope . 8
2 Terms and definitions . 8
3 Classification and class of the ECB . 8
4 Design rules and allowance . 9
4.1 Panel and board sizes . 9
4.1.1 Board size (for reference only) . 9
4.1.2 Allowance of dimensions . 10
4.1.3 Perforation and slit . 10
4.1.4 V-cut . 11
4.2 Total board thickness . 12
4.2.1 Total board thickness and its allowance . 12
4.3 Holes . 13
4.3.1 Insertion holes and vias . 13
4.3.2 Datum hole . 15
4.3.3 Assembly hole (a through-hole without wall plating) . 15
4.4 Conductor . 15
4.4.1 Width of conductor pattern and its allowance . 15
4.4.2 Distance between conductors and its allowance . 16
4.4.3 Distance between conductor and board edge . 17
4.4.4 Thickness of the insulating layer . 17
4.5 Printed contact . 18
4.5.1 Allowance of the distance between the centres of two adjacent
printed contacts . 18
4.5.2 Allowance of the terminal width of printed contacts . 18
4.5.3 Shift of the centre of printed contacts on front and back sides of a
board . 18
4.6 Footprint. 19
4.6.1 Allowance of the distance between the centers of two pads . 19
4.6.2 Allowance of the width of a pad . 19
4.6.3 Pad diameter and its allowance for BGA/CSP . 20
4.7 Fiducial mark and the mark for component positioning . 21
4.8 Interlayer connection . 22
5 Quality . 22
5.1 Gap between conductor and the wall of a component insertion hole or a
via . 22
5.2 Positional deviation between conductor layers of multilayer board . 22
5.3 Minimum land width . 22
5.4 Surface treatment . 24
5.4.1 Gold plating for printed contact . 24
5.4.2 Other surface treatment . 24
5.5 Defects of solder resist . 24
5.6 Symbol mark . 26
5.7 Appearance . 27
5.7.1 Conductor surface . 27
5.7.2 Between conductors . 27
6 Performance and test methods . 33
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PAS 62326-20 IEC:2011(E) – 3 –
6.1 Observation of component mounting for and vias . 33
6.1.1 Observation with standard conditions . 33
6.1.2 Observation after thermal shock test . 34
7 Marking, packaging and storage . 47
7.1 Marking on a product . 47
7.2 Marking on the package . 47
7.3 Packaging and storage . 47
7.3.1 Packaging . 47
7.3.2 Storage . 47
8 Normative references . 47
Annex A (informative) Additional information to IEC/PAS 62326-20. 48
Figure 1 – Example of classification and their application by base materials,
electronic circuit boards and final products . 9
Figure 2 – Board arrangement in a panel . 9
Figure 3 – Distances from the datum point to perforation and slit . 10
Figure 4 – Distance from the datum point to V-cut . 11
Figure 5 – Allowance of position off-set of V-cuts on front and back surfaces . 11
Figure 6 – PWB board with symbol mark, solder resist, copper foil and plating . 12
Figure 7 – Positions of component insertion holes . 13
Figure 8 – Distance between the wall of a hole to the board edge . 14
Figure 9 – Hole wall and the minimum designed spacing to the inner conductor . 15
Figure 10 – Width of finished conductor . 16
Figure 11 – Distance between finished conductors . 17
Figure 12 – Thickness of the insulating layer . 17
Figure 13 – Distance between centres of terminals of printed contacts . 18
Figure 14 – Terminal width of a printed contact . 18
Figure 15 – Shift of the centre of printed contacts on front and back sides of a board . 19
Figure 16 – Foot print . 19
Figure 17– Pad width of a footprint . 20
Figure 18 – Allowance of pad diameter of BGA/CSP formed of conductor only . 20
Figure 19 – Pad diameter (d) of BGA/CSP formed at the opening of solder resist . 21
Figure 20 – Examples of fiducial mark and component positioning mark . 21
Figure 21-1 – Minimum land width on the outer layer . 23
Figure 21-2 – Minimum land width on the inner layer with a plated through-hole . 23
Figure 21-3 – Allowable area of land break . 24
Figure 22 – Exposure of conductor . 25
Figure 23 – Minimum land width caused by the shift of solder resist . 25
Figure 24 – The overlap, smear and shift of solder resist . 26
Figure 25 – Examples . 26
Figure 26 – Example of measling . 27
Figure 27 – Examples of crazing . 28
Figure 28 – Missing of conductor . 28
Figure 29 – Conductor residue . 28
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– 4 – PAS 62326-20 IEC:2011(E)
Figure 30 – Land. 29
Figure 31 – Defects in a pad of a footprint . 29
Figure 32 – Defects in BGA/CSP mounting pads . 30
Figure 33 – The areas to be checked for defects of a printed contact . 31
Figure 34 – Defects in a printed contact . 31
Figure 35 – Defect on a plating of a component mounting hole . 33
Figure 36-1 – Resin smear . 34
Figure 36-2 – Corner crack . 35
Figure 36-3 – Barrel crack . 35
Figure 36-4 – Foil crack . 35
Figure 37 – The relations between resistance and width, thickness and temperature
of conductor . 36
Figure 38 – Temperature rise as functions of width and thickness of conductor and
current . 37
Table 1 – Application and classification . 8
Table 2 – Panel dimensions (informative purpose) . 10
Table 3– Allowance of dimensions . 10
Table 4 – Allowance of the distances from the datum point to perforation and slit . 11
Table 5 – Allowance for the distance from the datum point to the center of the V-cut . 12
Table 6 – Total thickness and its allowance . 12
Table 7 – Allowance of holes for component insertion . 13
Table 8 – Position allowance of component insertion holes . 13
Table 9 – Distance between a hole wall and board edge . 14
Table 10 – Minimum clearance between the hole wall and the inner layer conductor . 14
Table 11 – Allowance of conductor width . 16
Table 12 – Allowance of the distance between conductors . 16
Table 13 – Distance between conductor and board edge . 17
Table 14 – Allowance of the terminal width of a printed contact . 18
Table 15 – Allowance of the distance between the centres of two pads . 19
Table 16 – Allowance of the width of a pad of a footprint . 20
Table 17 – Pad diameter and its allowance for BGA/CSP . 20
Table 18 – Allowance of the pad diameter (d) of BGA/CSP formed at the opening of
solder resist . 21
Table 19 – Shapes and sizes of typical fiducial marks and component positioning
marks . 22
Table 20 – Minimum thickness of copper plating . 22
Table 21 – Minimum land width . 23
Table 22 – Minimum land width . 25
Table 23 – The overlap, smear and shift of solder resist over a fool print . 26
Table 24 – Allowance of the area of a defect, remaining width and protrusion of a
land . 29
Table 25 – Defect of a pad of a footprint . 30
Table 26 – Defects in BGA/CSP mounting pads . 30
Table 27 – Defects in a printed contact . 32
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PAS 62326-20 IEC:2011(E) – 5 –
Table 28 – Allowance in horizontal sectioning . 34
Table 29 – Specification and test methods . 38
Table A.1 – The relation between thermal conductive parameter (W/(mK)) and heat
transfer coefficient parameter . 49
Table A.2 – The relation between thermal conductive parameter (W/(mK)) and heat
transfer coefficient parameter . 49
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– 6 – PAS 62326-20 IEC:2011(E)
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
PRINTED BOARDS –
Part 20: Electronic circuit board for high-brightness LEDs
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization
comprising all national electrotechnical committees (IEC National Committees). The object of IEC is to
promote international co-operation on all questions concerning standardization in the electrical and
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referred to as “IEC Publication(s)”). Their preparation is entrusted to technical committees; any IEC National
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
A PAS is a technical specification not fulfilling the requirements for a standard, but made
available to the public.
IEC-PAS 62326-20 was submitted by the JPCA (Japan Electronics Packaging and Circuits
Association) and has been processed by IEC technical committee 91: Electronics assembly
technology.
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PAS 62326-20 IEC:2011(E) – 7 –
It is based on JPCA-TMC-LED01S-2010. It is published as a double-logo PAS and JPCA.
The text of this PAS is based on the This PAS was approved for
following document: publication by the P-members of the
committee concerned as indicated in
the following document
Draft PAS Report on voting
91/926/PAS 91/942A/RVD
Following publication of this PAS, which is a pre-standard publication, the technical
committee or subcommittee concerned may transform it into an International Standard.
This PAS shall remain valid for an initial maximum period of 3 years starting from the
publication date. The validity may be extended for a single period up to a maximum of
3 years, at the end of which it shall be published as another type of normative document, or
shall be withdrawn.
A list of all the parts in the IEC 62326 series, under the general title Printed boards, can be
found on the IEC website.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct
understanding of its contents. Users should therefore print this document using a
colour printer.
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– 8 – PAS 62326-20 IEC:2011(E)
PRINTED BOARDS –
Part 20: Electronic circuit board for high-brightness LEDs
1 Scope
This PAS specifies the properties of the electronic circuit board for high-brightness LEDs
(hereafter described as “ECB”).
NOTE Standards relevant to the present standards are given below.
JPCA-TD01 Terms and definitions for printed circuits
JIS C 5603 Terms and definitions for printed circuits
2 Terms and definitions
For the purpose of this document, the terms used in this PAS shall be in accordance with
JPCA-TD01 and JIS C 5603, unless otherwise specified.
3 Classification and class of the ECB
The ECB specified in this PAS shall satisfy the specification of (A) to (C) in Table 1 in the
following way. The materials used in the materials of PWB are not specified; however, they
shall be agreed upon between user and supplier depending on the application area of the
boards in question.
Table 1 – Application and classification
Small Thermal Heat
Classification
classification conductivity transfer
Definition
Definition
(thermal parameter parameter
(insulation
conductivity)
2
property) W/(mK) W/(m K)
I No specification
<1 <10
A Standard boards Ⅱ Electric strength <1,000 V
Ⅲ Electric strength 1,000 V≤
No specification
Ⅰ
Thermal
Electric strength <1,000 V
B conductive Ⅱ
boards
1≤ <10
Electric strength 1,000 V≤
Ⅲ
No specification
Ⅰ
High thermal
C conductive Ⅱ Electric strength <1,000 V
boards
1≤ 10≤
Electric strength 1,000 V≤
Ⅲ
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PAS 62326-20 IEC:2011(E) – 9 –
Heat Radiation A B C
Resin type substrate (CEM-3, FR-4, FR-5 ) Resin type substrate (with thermal via)
Flexible type substrate High thermal conductive resin substrate
Metal core substrate
Classsification by base materials
Metal base substrate
Ceramic type substrate
Conventional substrate for discreat type electronic parts mounted boards
Classification by electronic circuit boards Substrate for semiconductor package
Substrate for Chip on Board
Assistant lighting lamp
Lamp substitute for halogen lamp
Lamp substitute for fluorescent lamp substitution
Classification by final products
Lamp substitute for filament lamp
Street lamp
Lamp substitute for HID
Insulation class Ⅰ Ⅱ Ⅲ Ⅰ Ⅱ Ⅲ Ⅰ Ⅱ Ⅲ
Figure 1 – Example of classification and their application by base materials,
electronic circuit boards and final products
4 Design rules and allowance
4.1 Panel and board sizes
4.1.1 Board size (for reference only)
The size of the board of the product (axb) illustrated in Figure 2 shall be selected so that
the boards can be arranged efficiently within a panel with a size specified in Table 2. Or, a
proper panel with a size given in the table shall be selected so as to satisfy the required
efficient arrangement of the boards.
Table 1. PWB
Board size of the product: a x b
Space between board and
panel edges: c ，c ，c ，c
1 2 3 4
Space between boards: e ，e
1 2
Figure 2 – Board arrangement in a panel
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– 10 – PAS 62326-20 IEC:2011(E)
Table 2 – Panel dimensions (informative purpose)
mm
Division
Size of CCL (copper
clad laminate) panel
４ ６ ８ ９
1 000 × 1 000 500 × 500 333 × 500 250 × 500 333 × 333
333 × 600
1 000 × 1 200 500 × 600 300 × 500 333 × 400
400 × 500
4.1.2 Allowance of dimensions
The allowance of dimensions of a board or a panel is given in Table 3.
Table 3– Allowance of dimensions
mm
Longitudinal size Allowance
≤ 100 ±0,2
Add 0,1 for each 50 exceeding a length of 100.
100<
4.1.3 Perforation and slit
The perforation and slit are shown in Figure 3. The allowance of the distances from the
datum point to the center of the cut of the perforation and slit is given in Table 4.
Figure 3 – Distances from the datum point to perforation and slit
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PAS 62326-20 IEC:2011(E) – 11 –
Table 4 – Allowance of the distances from the datum point to perforation and slit
mm
Distances from the datum
Allowance
point to perforation and slit
≤ 100 ±0,2
100 < Add 0,1 for each 50 beyond a length of 100.
4.1.4 V-cut
The V-cut is shown in Figure 4. The allowance of the distance from the reference datum to
the center of cut of the V (g to g ) is given in Table 5. The allowance of the deviation of the
1 4
position of the V-cut on the front and back planes is 0,2 mm, and the allowance of the uncut
thickness of the board is the sum of the allowance of the board thickness ±0,1 mm.
Board Peripheral
V-cut
Datum point
Figure 4 – Distance from the datum point to V-cut
mm
Insulating board
Figure 5 – Allowance of position off-set of V-cuts on front and back surfaces
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– 12 – PAS 62326-20 IEC:2011(E)
Table 5 – Allowance for the distance from the datum point to the center of the V-cut
Distance from the datum
point to the center of the Allowance
V-cut
≤100 ±0,2
>100 Add 0,1 for each 50 mm exceeding a length over 100 mm
4.2 Total board thickness
4.2.1 Total board thickness and its allowance
The allowance of the total board thickness (t) of a board with solder resist and symbol
marks as shown in Figure 6 is given in Table 6.
Solder resist
Symbol mark
Plating
Copper foil
Figure 6 – PWB board with sy
...
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