Mechanical standardization of semiconductor devices - Part 6-20: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of small outline J-lead packages (SOJ) (IEC 60191-6-20:2010)

This part of IEC 60191 specifies methods to measure package dimensions of small outline Jlead- packages (SOJ), package outline form E in accordance with IEC 60191-4.

Mechanische Normung von Halbleiterbauelementen - Teil 6-20: Allgemeine Regeln für die Erstellung von Gehäusezeichnungen von SMD-Halbleitergehäusen - Messverfahren für Gehäusemaße von kleinen Gehäusen mit J-förmigen Anschlüssen (SOJ) (IEC 60191-6-20:2010)

Normalisation mécanique des dispositifs à semiconducteurs - Part 6-20: Règles générales pour la préparation des dessins d'encombrement des boîtiers pour dispositifs à semiconducteurs pour montage en surface - Méthodes de mesure pour les dimensions des boîtiers à sortie en J (SOJ) de faible encombrement (CEI 60191-6-20:2010)

La CEI 60191-6-20:2010 spécifie les méthodes destinées à mesurer les dimensions des boîtiers à sortie en J (SOJ) de faible encombrement, l'encombrement des boîtiers de forme E conformément à la CEI 60191-4.

Standardizacija mehanskih lastnosti polprevodniških elementov - 6-20. del: Splošna pravila za izdelavo tehničnih risb površinsko montiranih sklopov polprevodniških elementov - Merilne metode za mere majhnih okrovov s priključki v obliki črke J (SOJ) (IEC 60191-6-20:2010)

Ta del IEC 60191 določa metode za merjenje mer majhnih okrovov s priključki v obliki črke J (SOJ), okrovov v obliki črke E v skladu z IEC 60191-4.

General Information

Status
Published
Publication Date
17-Nov-2010
Technical Committee
Current Stage
6060 - National Implementation/Publication (Adopted Project)
Start Date
29-Oct-2010
Due Date
03-Jan-2011
Completion Date
18-Nov-2010

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SLOVENSKI STANDARD
SIST EN 60191-6-20:2010
01-december-2010
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Mechanical standardization of semiconductor devices - Part 6-20: General rules for the

preparation of outline drawings of surface mounted semiconductor device packages -

Measuring methods for package dimensions of small outline J-lead packages (SOJ) (IEC

60191-6-20:2010)

Mechanische Normung von Halbleiterbauelementen - Teil 6-20: Allgemeine Regeln für

die Erstellung von Gehäusezeichnungen von SMD-Halbleitergehäusen - Messverfahren

für Gehäusemaße von kleinen Gehäusen mit J-förmigen Anschlüssen (SOJ) (IEC 60191-

6-20:2010)
Normalisation mécanique des dispositifs à semiconducteurs - Part 6-20: Règles

générales pour la préparation des dessins d'encombrement des boîtiers pour dispositifs

à semiconducteurs pour montage en surface - Méthodes de mesure pour les dimensions

des boîtiers à sortie en J (SOJ) de faible encombrement (CEI 60191-6-20:2010)
Ta slovenski standard je istoveten z: EN 60191-6-20:2010
ICS:
01.100.25 5LVEHVSRGURþMD Electrical and electronics
HOHNWURWHKQLNHLQHOHNWURQLNH engineering drawings
31.080.01 Polprevodniški elementi Semiconductor devices in
(naprave) na splošno general
SIST EN 60191-6-20:2010 en

2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

---------------------- Page: 1 ----------------------
SIST EN 60191-6-20:2010
---------------------- Page: 2 ----------------------
SIST EN 60191-6-20:2010
EUROPEAN STANDARD
EN 60191-6-20
NORME EUROPÉENNE
October 2010
EUROPÄISCHE NORM
ICS 31.080.01
English version
Mechanical standardization of semiconductor devices -
Part 6-20: General rules for the preparation of outline drawings of surface
mounted semiconductor device packages -
Measuring methods for package dimensions of small outline J-lead
packages (SOJ)
(IEC 60191-6-20:2010)
Normalisation mécanique des dispositifs à Mechanische Normung von
semiconducteurs - Halbleiterbauelementen -
Part 6-20: Règles générales pour la Teil 6-20: Allgemeine Regeln für die
préparation des dessins d'encombrement Erstellung von Gehäusezeichnungen von
des boîtiers pour dispositifs à SMD-Halbleitergehäusen -
semiconducteurs pour montage en Messverfahren für Gehäusemaße von
surface - kleinen Gehäusen mit J-förmigen
Méthodes de mesure pour les dimensions Anschlüssen (SOJ)
des boîtiers à sortie en J (SOJ) de faible (IEC 60191-6-20:2010)
encombrement
(CEI 60191-6-20:2010)

This European Standard was approved by CENELEC on 2010-10-01. CENELEC members are bound to comply

with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard

the status of a national standard without any alteration.

Up-to-date lists and bibliographical references concerning such national standards may be obtained on

application to the Central Secretariat or to any CENELEC member.

This European Standard exists in three official versions (English, French, German). A version in any other

language made by translation under the responsibility of a CENELEC member into its own language and notified

to the Central Secretariat has the same status as the official versions.

CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus,

the Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy,

Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia,

Spain, Sweden, Switzerland and the United Kingdom.
CENELEC
European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung
Management Centre: Avenue Marnix 17, B - 1000 Brussels

© 2010 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members.

Ref. No. EN 60191-6-20:2010 E
---------------------- Page: 3 ----------------------
SIST EN 60191-6-20:2010
EN 60191-6-20:2010 - 2 -
Foreword

The text of document 47D/771/FDIS, future edition 1 of IEC 60191-6-20, prepared by SC 47D,

Mechanical standardization for semiconductor devices, of IEC TC 47, Semiconductor devices, was

submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN 60191-6-20 on

2010-10-01.

Attention is drawn to the possibility that some of the elements of this document may be the subject of

patent rights. CEN and CENELEC shall not be held responsible for identifying any or all such patent

rights.
The following dates were fixed:
– latest date by which the EN has to be implemented
at national level by publication of an identical
national standard or by endorsement (dop) 2011-07-01
– latest date by which the national standards conflicting
with the EN have to be withdrawn (dow) 2013-10-01
Annex ZA has been added by CENELEC.
__________
Endorsement notice

The text of the International Standard IEC 60191-6-20:2010 was approved by CENELEC as a European

Standard without any modification.
__________
---------------------- Page: 4 ----------------------
SIST EN 60191-6-20:2010
- 3 - EN 60191-6-20:2010
Annex ZA
(normative)
Normative references to international publications
with their corresponding European publications

The following referenced documents are indispensable for the application of this document. For dated

references, only the edition cited applies. For undated references, the latest edition of the referenced

document (including any amendments) applies.

NOTE When an international publication has been modified by common modifications, indicated by (mod), the relevant EN/HD

applies.
Publication Year Title EN/HD Year
IEC 60191-4 - Mechanical standardization of semiconductor EN 60191-4 -
devices -
Part 4: Coding system and classification into
forms of package outlines for semiconductor
device packages
IEC 60191-6 - Mechanical standardization of semiconductor EN 60191-6 -
devices -
Part 6: General rules for the preparation of
outline drawings of surface mounted
semiconductor device packages
---------------------- Page: 5 ----------------------
SIST EN 60191-6-20:2010
---------------------- Page: 6 ----------------------
SIST EN 60191-6-20:2010
IEC 60191-6-20
Edition 1.0 2010-08
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Mechanical standardization of semiconductor devices –
Part 6-20: General rules for the preparation of outline drawings of surface
mounted semiconductor device packages – Measuring methods for package
dimensions of small outline J-lead packages (SOJ)
Normalisation mécanique des dispositifs à semiconducteurs –
Partie 6-20: Règles générales pour la préparation des dessins d'encombrement
des boîtiers pour dispositifs à semiconducteurs pour montage en surface –
Méthodes de mesure pour les dimensions des boîtiers à sortie en J (SOJ) de
faible encombrement
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
CODE PRIX
ICS 31.080.01 ISBN 978-2-88912-167-0
® Registered trademark of the International Electrotechnical Commission
Marque déposée de la Commission Electrotechnique Internationale
---------------------- Page: 7 ----------------------
SIST EN 60191-6-20:2010
– 2 – 60191-6-20 © IEC:2010
INTERNATIONAL ELECTROTECHNICAL COMMISSION
______________
MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES –
Part 6-20: General rules for the preparation of outline drawings
of surface mounted semiconductor device packages –
Measuring methods for package dimensions
of small outline J-lead packages (SOJ)
FOREWORD

1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising

all national electrotechnical committees (IEC National Committees). The object of IEC is to promote

international co-operation on all questions concerning standardization in the electrical and electronic fields. To

this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,

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agreement between the two organizations.

2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international

consensus of opinion on the relevant subjects since each technical committee has representation from all

interested IEC National Committees.

3) IEC Publications have the form of recommendations for international use and are accepted by IEC National

Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC

Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any

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4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications

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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is

indispensable for the correct application of this publication.

9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of

patent rights. IEC shall not be held responsible for identifying any or all such patent rights.

International Standard IEC 60191-6-20 has been prepared by subcommittee 47D: Mechanical

standardization of semiconductor devices, of IEC technical committee 47: Semiconductor

devices.
The text of this standard is based on the following documents:
FDIS Report o
...

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