This document specifies standard aspect ratios for logarithmic or level characteristics
expressed in decibels versus a logarithmic frequency axis and ranges for the radius of polar
diagrams of level. Applications include hard copy printouts, electronic files (e.g., PDF files),
scientific publications, screen displays in computer programs and apps, as well as graphs in
standards.
Informative examples of graphs that conform to the requirements in this document are found in
Annex A.
Although outside the scope of this document, graphs with a linear y-axis versus logarithmic
frequency (e.g., phase, group delay, etc.) often accompany the standard aspect ratio graphs of
level described in the normative part of this document. These are described in informative
Annex B.

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This standard specifies generic requirements for dimensional drawings of SMD from the viewpoint of land pattern design. The purpose of this document is to prevent land pattern design issues caused by lack of information and/or misuse of the information from SMD outline drawing as well as to improve the utilization of IEC 61188 series. This document is applicable to the SMD of semiconductor devices and electrical components.

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This part of IEC 60191 gives guidelines on the preparation of outline drawings of discrete
devices, including discrete surface-mounted semiconductor devices with lead count less than
8.
For the preparation of outline drawings of surface-mounted discrete devices with a lead count
higher or equal to 8, IEC 60191-6 should be referred to as well.
The primary object of these drawings is to indicate the space to be allowed for devices in
equipment, together with other dimensional characteristics required to ensure mechanical
interchangeability.
Complete interchangeability involves other considerations such as the electrical and thermal
characteristics of the semiconductor devices concerned.
The international standardization represented by these drawings therefore encourages the
manufacturers of devices to comply with the tolerances shown on the drawings in order to
extend their range of customers internationally. It also gives equipment designers an
assurance of mechanical interchangeability between the devices obtained from suppliers in
different countries, provided they allow the space in their equipment that is indicated by the
drawings and take note of the more precise information on bases, studs, etc.
NOTE Additional details of reference letter symbols used in this document are given in Annex A.

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This International Standard defines the GRAFCET1 specification language for the functional description of the behaviour of the sequential part of a control system. This standard specifies the symbols and rules for the graphical representation of this language, as well as for its interpretation. This standard has been prepared for automated production systems of industrial applications. However, no particular area of application is excluded. Methods of development of a specification that makes use of GRAFCET are beyond the scope of this standard. One method is for example the "SFC language" specified in IEC 61131-3, which defines a set of programming languages for programmable controllers.

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This part of IEC 60191 provides standard outline drawings, dimensions, and recommended variations for all fine-pitch land grid array packages (FLGA) with terminal pitch of 0,8 mm or less.

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This part of IEC 60191 specifies methods to measure package dimensions of small outline Jlead- packages (SOJ), package outline form E in accordance with IEC 60191-4.

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This part of IEC 60191 specifies methods to measure package dimensions of small outline packages (SOP), package outline form E in accordance to IEC 60191-4.

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This part of IEC 60191 specifies measurement methods of the package warpage at elevated temperature and the maximum permissible warpages for Ball Grid Array(BGA), Fine-pitch Ball Grid Array (FBGA), and Fine-pitch Land Grid Array (FLGA).

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This part of IEC 60191 provides standard outline drawings, dimensions, and recommended variations for all square ball grid array packages (BGA), whose terminal pitch is 1 mm or larger.

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This part of IEC 60191 gives general rules for the preparation of outline drawings of surfacemounted semiconductor devices. It supplements IEC 60191-1 and IEC 60191-3. It covers all surface-mounted devices discrete semiconductors with lead count of greater or equal to 8, as well as integrated circuits classified as form E in Clause 3 of IEC 60191-4.

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This part of IEC 60191 gives a glossary of semiconductor sockets for BGA, LGA, FBGA and FLGA. This standard intends to establish definitions and unification of terminology relating to tests and burn-in sockets for BGA, LGA, FBGA and FLGA.

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Covers the requirements for the design rule of terminal shape plastic packages with gull-wing leads; e.g., QFP, SOP, SSOP, TSOP, etc. which are packages classified as Form E in IEC 60191-4. This publication is intended to establish common rules on terminal shapes irrespective of package types.

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Provides the common outline drawings and dimensions for all types of structures and composed materials of plastic very thin small outline non-lead package (P-VSON).

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EN following parallel vote * Supersedes HD 147 S1:1977

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This part of IEC 60191 gives guidelines on the preparation of outline drawings of discrete devices. The primary object of these drawings is to indicate the space which should be allowed for devices in an equipment, together with other dimensional characteristics required to ensure mechanical interchangeability. It should be noted that complete interchangeability involves other considerations such as the electrical and thermal characteristics of the semiconductor devices concerned. The international standardization represented by these drawings therefore encourages the manufacturers of devices to comply with the tolerances shown on the drawings in order to extend their range of customers internationally. It also gives equipment designers an assurance of mechanical interchangeability between the devices obtained from suppliers in different countries, provided they allow the space in their equipment that is indicated by the drawings and take note of the more precise information on bases, studs, etc.

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This part of IEC 60191 gives a design guideline of open-top-type semiconductor sockets for Fine-pitch Ball Grid Array ("FBGA" hereafter) and Fine-pitch Land Grid Array ("FLGA" hereafter). This standard is intended to establish the outline drawings and dimensions of the open-top-type socket out of the test and burn-in sockets applied to FBGA and FLGA.

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EN following parallel vote

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Gives general rules for the preparation of outlines drawings of surface-mounted semiconductor devices. It supplements EN 60191-1 and 60191-3. It covers all surface-mounted discrete semiconductors devices as well as integrated circuits classified as form E.

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