SIST EN 60191-6-21:2010

• Abstract:

  IEC 60191-6-21:2010 specifies methods to measure package dimensions of small outline packages (SOP), package outline form E in accordance to IEC 60191-4.

• Status: Published
• Publication Date: 15-Nov-2010
• ICS: 01.100.25 - Electrical and electronics engineering drawings
• ICS: 31.080.01 - Semiconductor devices in general
• ICS: 31.240 - Mechanical structures for electronic equipment
• Technical Committee: I11 - Imaginarni 11
• Current Stage: 6060 - National Implementation/Publication (Adopted Project)
• Start Date: 29-Oct-2010
• Due Date: 03-Jan-2011
• Completion Date: 16-Nov-2010
• Ref Project: EN 60191-6-21:2010 - Mechanical standardization of semiconductor devices - Part 6-21: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of small outline packages (SOP)

• Refers: SIST EN 60191-6:2010 - Mechanical standardization of semiconductor devices -- Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages (IEC 60191-6:2009)
• Effective Date: 03-Feb-2026
• Refers: SIST EN 60191-4:2002 - Mechanical standardization of semiconductor devices -- Part 4: Coding system and classification into forms of package outlines for semiconductor device packages
• Effective Date: 03-Feb-2026
• Referred By: SIST EN IEC 60191-1:2018 - Mechanical standardization of semiconductor devices - Part 1: General rules for the preparation of outline drawings of discrete devices (IEC 60191-1:2018)
• Effective Date: 03-Feb-2026

SIST EN 60191-6-21:2010 is the Slovenian adoption of EN 60191-6-21:2010, which CENELEC approved as identical to IEC 60191-6-21:2010. It specifies methods for measuring package dimensions of small outline packages (SOP), package outline form E, for use in preparing and checking outline drawings of surface mounted semiconductor device packages.

What does SIST EN 60191-6-21:2010 specify?

SIST EN 60191-6-21:2010 defines how to measure the dimensions of SOP packages so that the values used in outline drawings are consistent. The document is organized into a scope, normative references, terms and definitions, and measuring methods, with Annex ZA giving the normative references to other publications.

Annex	What it covers
ZA	Normative references to IEC 60191-4 and IEC 60191-6

The scope is limited to SOP, identified as package outline form E in accordance with IEC 60191-4. That matters because the methods are intended for one package family and its drawing conventions, not for all semiconductor package types.

What are the key requirements of SIST EN 60191-6-21:2010?

SIST EN 60191-6-21:2010 focuses on measurement practice, not on electrical performance. Clause 4 gives the methods for the package dimensions that are normally supplied to users and shown on outline drawings.

General measuring approach

Clause 4.1 states that package dimensions are generally measured with the semiconductor package mounted on a printed circuit-board, because that reflects the condition in which the user receives it. The measurements may be done by hand or automatically, so the method can be adapted to lab checks or production inspection. If a dimension cannot be measured without destroying the package, it may be calculated from other dimensions or replaced by a representative value.

Package body dimensions

Clauses 4.3, 4.4 and 4.5 define how to measure mounting height A, stand-off A1 and body thickness A2. In practice, these measurements establish the package height above the seating plane and the thickness of the body, which are needed to verify clearance, stacking and board-level fit.

Lead dimensions and soldered portion length

Clause 4.6 covers lead widths bp and b1, and lead thickness c and c1, including before-plating and after-plating values. Clause 4.7 covers soldered portion length Lp. These measurements matter because they describe the lead geometry used for soldering and for compatibility with PCB footprints.

Lead position and coplanarity

Clause 4.8 defines positional tolerance of terminal tips, based on the difference between the actual lead centers and their theoretical positions. Clause 4.9 defines coplanarity y of the lowest surfaces of the leads, and also gives a virtual plane method to handle seesaw effects. This is important for mounting reliability, because uneven leads can affect soldering and board contact.

Lead angle

Clause 4.10 defines the angle θ of the flat portion of a gull wing lead and gives a measuring method based on two height points near the tip. The clause also allows a virtual plane method and says side observation may be used as representative data. This helps verify lead forming for solderability and package consistency.

What terms does SIST EN 60191-6-21:2010 define?

• Small outline packages (SOP) - The package family covered by this standard.
• Package outline form E - The SOP outline form identified by IEC 60191-4.
• Mounting height A - The height from the seating plane to the top of the package.
• Stand-off A1 - The distance from the seating plane to the lowest point of the package.
• Coplanarity y - The vertical distance to the lowest lead point furthest from the seating plane.
• Virtual plane - A plane through three lowest lead points that supports coplanarity measurement when needed.
• Soldered portion length Lp - The lead length measured in the mounting direction from the reference crossing point to the lead tip.

Who uses SIST EN 60191-6-21:2010?

SIST EN 60191-6-21:2010 is used by semiconductor device manufacturers, package-drawing engineers, and mechanical design teams that prepare outline drawings for surface mounted packages. It is also relevant to quality control, inspection laboratories, and purchasing or supplier-management teams that need a common way to check package dimensions against drawing data.

In practice, these users apply the standard when they measure sample packages, compare vendor data, or define the mechanical envelope for PCB assembly and land-pattern design.

Which standards are used with SIST EN 60191-6-21:2010?

Annex ZA names the documents needed with this standard:

• IEC 60191-4 - provides the coding system and classification into forms of package outlines for semiconductor device packages.
• IEC 60191-6 - gives the general rules for preparing outline drawings of surface mounted semiconductor device packages and supplies the terms used here.

What does the SIST EN 60191-6-21:2010 document contain?

The document contains outline drawings for TSOP(1), SSOP and TSOP(2), together with the measurement references used in each case. It also includes figures showing mounting height, stand-off, body thickness, lead widths and thicknesses, soldered portion length, terminal tip tolerance, coplanarity, the virtual plane method, and the angle θ measurement points.

Clause 4 describes how to take each measurement, usually from the surface plate, from the side, or from the top depending on the feature. The document also states when representative values may be used, such as for lead thickness or side-observable lead values. For users, this means the standard is a practical measurement guide for package drawings, inspection, and dimensional verification.

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Mechanical standardization of semiconductor devices - Part 6-21: General rules for the
preparation of outline drawings of surface mounted semiconductor device packages -
Measuring methods for package dimensions of small outline packages (SOP) (IEC
60191-6-21:2010)
Mechanische Normung von Halbleiterbauelementen - Teil 6-21: Allgemeine Regeln für
die Erstellung von Gehäusezeichnungen von SMD-Halbleitergehäusen - Messverfahren
für Gehäusemaße von kleinen Gehäusen (SOP) (IEC 60191-6-21:2010)
Normalisation mécanique des dispositifs à semiconducteurs - Part 6-21: Règles
générales pour la préparation des dessins d'encombrement des boîtiers pour dispositifs
à semiconducteurs pour montage en surface - Méthodes de mesure pour les dimensions
des boîtiers de faible encombrement (SOP) (CEI 60191-6-21:2010)
Ta slovenski standard je istoveten z: EN 60191-6-21:2010
ICS:
01.100.25 5LVEHVSRGURþMD Electrical and electronics
HOHNWURWHKQLNHLQHOHNWURQLNH engineering drawings
31.080.01 Polprevodniški elementi Semiconductor devices in
(naprave) na splošno general
31.240 Mehanske konstrukcije za Mechanical structures for
elektronsko opremo electronic equipment
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

EUROPEAN STANDARD
EN 60191-6-21
NORME EUROPÉENNE
October 2010
EUROPÄISCHE NORM
ICS 31.080.01
English version
Mechanical standardization of semiconductor devices -
Part 6-21: General rules for the preparation of outline drawings of surface
mounted semiconductor device packages -
Measuring methods for package dimensions of small outline packages
(SOP)
(IEC 60191-6-21:2010)
Normalisation mécanique des dispositifs à Mechanische Normung von
semiconducteurs - Halbleiterbauelementen -
Part 6-21: Règles générales pour la Teil 6-21: Allgemeine Regeln für die
préparation des dessins d'encombrement Erstellung von Gehäusezeichnungen von
des boîtiers pour dispositifs à SMD-Halbleitergehäusen -
semiconducteurs pour montage en Messverfahren für Gehäusemaße von
surface - kleinen Gehäusen (SOP)
Méthodes de mesure pour les dimensions (IEC 60191-6-21:2010)
des boîtiers de faible encombrement
(SOP)
(CEI 60191-6-21:2010)
This European Standard was approved by CENELEC on 2010-10-01. CENELEC members are bound to comply
with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard
the status of a national standard without any alteration.

Up-to-date lists and bibliographical references concerning such national standards may be obtained on
application to the Central Secretariat or to any CENELEC member.

This European Standard exists in three official versions (English, French, German). A version in any other
language made by translation under the responsibility of a CENELEC member into its own language and notified
to the Central Secretariat has the same status as the official versions.

CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus,
the Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy,
Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia,
Spain, Sweden, Switzerland and the United Kingdom.
CENELEC
European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung

Management Centre: Avenue Marnix 17, B - 1000 Brussels

© 2010 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members.
Ref. No. EN 60191-6-21:2010 E
Foreword
The text of document 47D/772/FDIS, future edition 1 of IEC 60191-6-21, prepared by SC 47D,
Mechanical standardization for semiconductor devices, of IEC TC 47, Semiconductor devices, was
submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN 60191-6-21 on
2010-10-01.
Attention is drawn to the possibility that some of the elements of this document may be the subject of
patent rights. CEN and CENELEC shall not be held responsible for identifying any or all such patent
rights.
The following dates were fixed:
– latest date by which the EN has to be implemented
at national level by publication of an identical
national standard or by endorsement (dop) 2011-07-01
– latest date by which the national standards conflicting
with the EN have to be withdrawn (dow) 2013-10-01
Annex ZA has been added by CENELEC.
__________
Endorsement notice
The text of the International Standard IEC 60191-6-21:2010 was approved by CENELEC as a European
Standard without any modification.
__________
- 3 - EN 60191-6-21:2010
Annex ZA
(normative)
Normative references to international publications
with their corresponding European publications

The following referenced documents are indispensable for the application of this document. For dated
references, only the edition cited applies. For undated references, the latest edition of the referenced
document (including any amendments) applies.

NOTE  When an international publication has been modified by common modifications, indicated by (mod), the relevant EN/HD
applies.
Publication Year Title EN/HD Year

IEC 60191-4 - Mechanical standardization of semiconductor EN 60191-4 -
devices -
Part 4: Coding system and classification into
forms of package outlines for semiconductor
device packages
IEC 60191-6 - Mechanical standardization of semiconductor EN 60191-6 -
devices -
Part 6: General rules for the preparation of
outline drawings of surface mounted
semiconductor device packages
IEC 60191-6-21 ®
Edition 1.0 2010-08
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Mechanical standardization of semiconductor devices –
Part 6-21: General rules for the preparation of outline drawings of surface
mounted semiconductor device packages – Measuring methods for package
dimensions of small outline packages (SOP)

Normalisation mécanique des dispositifs à semiconducteurs –
Partie 6-21: Règles générales pour la préparation des dessins d'encombrement
des boîtiers pour dispositifs à semiconducteurs pour montage en surface –
Méthodes de mesure pour les dimensions des boîtiers de faible encombrement
(SOP)
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
N
CODE PRIX
ICS 31.080.01 ISBN 978-2-88912-168-7
– 2 – 60191-6-21 © IEC:2010
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES –

Part 6-21: General rules for the preparation of outline drawings
of surface mounted semiconductor device packages –
Measuring methods for package dimensions
of small outline packages (SOP)

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60191-6-21 has been prepared by subcommittee 47D: Mechanical
standardization of semiconductor devices, of IEC technical committee 47: Semiconductor
devices.
The text of this standard is based on the following documents:
FDIS Report on voting
47D/772/FDIS 47D/776/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.

60191-6-21 © IEC:2010 – 3 –
A list of all the parts in the IEC 60191 series, under the general title Mechanical
standardization of semiconductor devices, can be found on the IEC website.
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
– 4 – 60191-6-21 © IEC:2010
MECHANICAL STANDARDIZ
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