kSIST FprEN IEC 60747-15:2024

Semiconductor devices - Part 15: Discrete devices - Isolated power semiconductor devices

IEC 60747-15:2024 gives the requirements for isolated power semiconductor devices. These requirements are additional to those given in other parts of IEC 60747 for the corresponding non-isolated power devices and parts of IEC 60748 for ICs. This third edition includes the following significant technical changes with respect to the previous edition:
a) The intelligent power semiconductor modules (IPM), which was previously excluded from the first and second edition, is now included in this document (Annex C);
b) The thermal resistance is described for each switch (6.2.4);
c) Added isolation test between temperature sensor and terminals, in case there is an agreement with the user (6.1.2).

Halbleiterbauelemente - Einzel-Halbleiterbauelemente - Teil 15: Isolierte Leistungshalbleiter

Dispositifs à semiconducteurs - Partie 15: Dispositifs discrets - Dispositifs de puissance à semiconducteurs isolés

IEC 60747-15:2024 est disponible sous forme de IEC 60747-15:2024 RLV qui contient la Norme internationale et sa version Redline, illustrant les modifications du contenu technique depuis l'édition précédente.
L'IEC 60747-15:2024 spécifie les exigences relatives aux dispositifs de puissance à semiconducteurs isolés. Ces exigences s’ajoutent à celles qui figurent dans d’autres parties de l’IEC 60747 pour les dispositifs de puissance non isolés correspondants et dans des parties de l’IEC 60748 pour les circuits intégrés. Cette troisième édition inclut les modifications techniques majeures suivantes par rapport à l’édition précédente:
a) les modules de puissance à semiconducteurs intelligents (IPM, Intelligent Power semiconductor Module), qui étaient auparavant exclus des première et deuxième éditions, sont désormais inclus dans le présent document (Annexe C);
b) la résistance thermique est décrite pour chaque interrupteur (6.2.4);
c) ajout d’un essai d’isolement entre le capteur de température et les bornes, en cas d’accord avec l’utilisateur (6.1.2).

Polprevodniški elementi - 15. del: Diskretni elementi - Izolirani močnostni polprevodniški elementi

General Information

• Status: Not Published
• Public Enquiry End Date: 31-Oct-2023
• ICS: 31.080.01 - Semiconductor devices in general
• ICS: 31.080.99 - Other semiconductor devices
• Technical Committee: I11 - Imaginarni 11
• Current Stage: 5020 - Formal vote (FV) (Adopted Project)
• Start Date: 08-May-2024
• Due Date: 26-Jun-2024
• Completion Date: 09-May-2024
• Ref Project: FprEN IEC 60747-15:2024 - Semiconductor devices - Part 15: Discrete devices - Isolated power semiconductor devices

Relations

• Revises: SIST EN 60747-15:2012 - Semiconductor devices - Discrete devices - Part 15: Isolated power semiconductor devices
• Effective Date: 23-Jan-2023

Standards Content (Sample)

SLOVENSKI STANDARD
oSIST prEN IEC 60747-15:2023
01-oktober-2023
Polprevodniški elementi - 15. del: Diskretni elementi - Izolirani močnostni
polprevodniški elementi
Semiconductor devices - Part 15: Discrete devices - Isolated power semiconductor
devices
Halbleiterbauelemente - Einzel-Halbleiterbauelemente - Teil 15: Isolierte
Leistungshalbleiter
Dispositifs à semiconducteurs - Partie 15: Dispositifs discrets - Dispositifs de puissance à
semiconducteurs isolés
Ta slovenski standard je istoveten z: prEN IEC 60747-15:2023
ICS:
31.080.01 Polprevodniški elementi Semiconductor devices in
(naprave) na splošno general
oSIST prEN IEC 60747-15:2023 en
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

oSIST prEN IEC 60747-15:2023
oSIST prEN IEC 60747-15:2023
47E/812/CDV
COMMITTEE DRAFT FOR VOTE (CDV)
PROJECT NUMBER:
IEC 60747-15 ED3
DATE OF CIRCULATION: CLOSING DATE FOR VOTING:
2023-08-18 2023-11-10
SUPERSEDES DOCUMENTS:
47E/792/CD, 47E/800/CC
IEC SC 47E : DISCRETE SEMICONDUCTOR DEVICES
SECRETARIAT: SECRETARY:
Korea, Republic of Mr Hojun Ryu
OF INTEREST TO THE FOLLOWING COMMITTEES: PROPOSED HORIZONTAL STANDARD:

Other TC/SCs are requested to indicate their interest, if
any, in this CDV to the secretary.
FUNCTIONS CONCERNED:
EMC ENVIRONMENT QUALITY ASSURANCE SAFETY
SUBMITTED FOR CENELEC PARALLEL VOTING NOT SUBMITTED FOR CENELEC PARALLEL VOTING
Attention IEC-CENELEC parallel voting
The attention of IEC National Committees, members of
CENELEC, is drawn to the fact that this Committee Draft
for Vote (CDV) is submitted for parallel voting.
The CENELEC members are invited to vote through the
CENELEC online voting system.
This document is still under study and subject to change. It should not be used for reference purposes.
Recipients of this document are invited to submit, with their comments, notification of any relevant patent rights of
which they are aware and to provide supporting documentation.
Recipients of this document are invited to submit, with their comments, notification of any relevant “In Some
Countries” clauses to be included should this proposal proceed. Recipients are reminded that the CDV stage is
the final stage for submitting ISC clauses. (SEE AC/22/2007 OR NEW GUIDANCE DOC).

TITLE:
Semiconductor devices - Part 15: Discrete devices - Isolated power semiconductor devices

PROPOSED STABILITY DATE: 2029
NOTE FROM TC/SC OFFICERS:
The order of titles is changed for consistency with other IEC 60747 series.

download this electronic file, to make a copy and to print out the content for the sole purpose of preparing National
Committee positions. You may not copy or "mirror" the file or printed version of the document, or any part of it,
for any other purpose without permission in writing from IEC.

oSIST prEN IEC 60747-15:2023
IEC CDV 60747-15 © IEC 2023 2 47E/812/CDV

1 CONTENTS
3 FOREWORD. 5
4 1 Scope . 7
5 2 Normative references . 7
6 3 Terms and definitions . 8
7 4 Letter symbols . 9
8 4.1 General . 9
9 4.2 Additional subscripts/symbols . 9
10 4.3 List letter symbols . 9
11 4.3.1 Voltages and currents . 9
12 4.3.2 Mechanical symbols . 9
13 4.3.3 Other symbols . 10
14 5 Essential ratings (limiting values) and characteristics . 10
15 5.1 General . 10
16 5.2 Ratings (limiting values) . 10
17 5.2.1 Isolation voltage or Isolation test voltage (V ) . 10
isol
18 5.2.2 Peak case non-rupture current (where appropriate). 10
19 5.2.3 Terminal current (I ) (where appropriate), . 10
tRMS
20 5.2.4 Temperatures . 10
21 5.2.5 Mechanical ratings . 11
22 5.2.6 Climatic ratings (where appropriate) . 11
23 5.3 Characteristics . 11
24 5.3.1 Mechanical characteristics . 11
25 5.3.2 Parasitic inductance (L ) . 12
p
26 5.3.3 Parasitic capacitances (C ) . 12
p
27 5.3.4 Partial discharge inception voltage (V or V ) (where appropriate) . 12
iM i(RMS)
28 5.3.5 Partial discharge extinction voltage (V or V ) (where
eM e(RMS)
29 appropriate) . 12
30 5.3.6 Thermal resistances . 12
31 5.3.7 Transient thermal impedance (Z ) . 13
th
32 6 Measurement methods . 13
33 6.1 Verification of isolation voltage rating . 13
34 6.1.1 Verification of isolation voltage rating between terminals and base plate
35 (V ) . 13
isol
36 6.1.2 Verification of isolation voltage rating between temperature sensor and
37 terminals (V ) . 14
isol1
38 6.2 Methods of measurement . 15
39 6.2.1 Partial discharge inception and extinction voltages (V ) (V ) . 15
i e
40 6.2.2 Parasitic inductance (L ) . 15
p
41 6.2.3 Parasitic capacitance terminal to case (C ) . 17
p
42 6.2.4 Thermal characteristics . 18
43 7 Acceptance and reliability . 21
44 7.1 General requirements . 21
45 7.2 List of endurance tests . 21
46 7.3 Acceptance defining criteria . 21

oSIST prEN IEC 60747-15:2023
IEC CDV 60747-15 © IEC 2023 3 47E/812/CDV

47 7.4 Type tests and routine tests . 21
48 7.4.1 Type tests . 21
49 7.4.2 Routine tests . 22
50 Annex A (informative) Test method of peak case non-rupture current . 23
51 Annex B (informative) Measuring method of the thickness of thermal compound paste . 26
52 Annex C (informative) Intelligent power semiconductor modules (IPM) . 27
53 C.1 General . 27
54 C.2 Control terminals of IPM . 27
55 C.3 Essential ratings (limiting value) and characteristics. 28
56 C.3.1 General . 28
57 C.3.2 Ratings (limiting value) and testing method . 28
58 C.3.2.1 Supply voltage V / V . 28
D CC
59 C.3.2.2 Input voltage V / Input signal voltage V . 28
CIN in
60 C.3.2.3 Fault output voltage V / Alarm signal voltage V . 28
FO ALM
61 C.3.2.4 Fault output current I / Alarm signal current I . 29
FO ALM
62 C.3.2.5 Main circuit DC bus voltage at short circuit V . 31
SC
63 C.3.2.6 Acceptance defining criteria . 33
64 C.3.3 Characteristics and measuring method . 34
65 C.3.3.1 Turn-off times and turn-off switching energy at inductive load . 34
66 C.3.3.2 Turn-on times and turn-on switching energy at inductive load . 36
67 C.3.3.3 Control circuit current of upper arm I / I , and control circuit current
D CCP
68 of lower arm I / I . 37
D CCN
69 C.3.3.4 Input ON threshold voltage V / V , and input OFF threshold
th(on) inth(on)
70 voltage V / V . 39
th(off) inth(off)
71 C.3.3.5 Over current protection level I / Short circuit trip level SC . 40
OC
72 C.3.3.6 Over current protection delay time t / Short circuit current delay time
doc
73 t . 42
off(SC)
74 C.3.3.7 Over temperature protection OT / overheating protection temperature
75 level T , and over temperature protection hysteresis OT /
jOH (hys)
76 overheating protection hysteresis T . 44
jH
77 C.3.3.8 Control circuit under-voltage protection UV / Under-voltage protection
78 level V , control circuit under-voltage protection reset level UV /
UV r
79 Under-voltage protection hysteresis V , and fault output pulse width t
H FO
80 / alarm signal hold time t . 47
ALM
81 C.3.3.9 Fault output current I (during unprotection), I (during
FO(H) FO(L)
82 protection), and alarm signal current limiting resistance value R . 48
ALM
83 C.3.3.10 Common mode noise withstand capability . 50
84 Bibliography . 53
86 Figure 1 – Basic circuit diagram for isolation breakdown withstand voltage test (“high
87 pot test”) with V . 13
isol
88 Figure 2 – Basic circuit diagram for isolation voltage test between temperature sensor
89 and terminals (V ). 15
isol1
90 Figure 3 – Circuit diagram for measurement of parasitic inductances (L ) . 16
p
91 Figure 4 – Wave forms . 17
92 Figure 5 – Circuit diagram for measurement of parasitic capacitance (C ) . 18
p
oSIST prEN IEC 60747-15:2023
IEC CDV 60747-15 © IEC 2023 4 47E/812/CDV

93 Figure 6 – Cross-section of an isolated power device with reference points for
94 temperature measurement of T and T . 19
c s
95 Figure A.1 – Circuit diagram for test of peak case non-rupture current . 23
96 Figure B.1 – Example of a measuring gauge for a layer of thermal compound paste of
97 a thickness between 5 m and 150 m . 26
98 Figure C.1 – Example of internal circuit configuration block diagram of IPM . 27
99 Figure C.2 – Testing circuit for supply voltage, Input voltage / Input signal voltage, and
100 Fault output voltage / Alarm signal voltage . 29
101 Figure C.3 – Testing circuit for Fault output current / Alarm signal current . 30
102 Figure C.4 – Testing circuit for main circuit DC bus voltage at short circuit . 32
103 Figure C.5 – Waveforms of short circuit protection function . 33
104 Figure C.6 – Measurement circuit for switching times and switching energy at inductive
105 load (lower arm device measurement) . 35
106 Figure C.7
...