SIST EN 60191-6-5:2002

Mechanical standardization of semiconductor devices -- Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch ball grid array (FBGA)

Provides common outline drawings and dimensions for all types of structures and composed materials of fine-pitch ball grid array the terminal pitch of which is less than or equal to 0,80 mm.

Mechanische Normung von Halbleiterbauelemente -- Teil 6-5: Allgemeine Regeln für die Erstellung von Gehäusezeichnungen von SMD-Halbleitergehäusen - Konstruktionsleitfaden für Feinraster-Ball-Grid-Arrays (FBGA)

Normalisation mécanique des dispositifs à semiconducteurs -- Partie 6-5: Règles générales pour la préparation des dessins d'encombrement des dispositifs à semiconducteurs à montage en surface - Guide de conception pour les boîtiers matriciels à billes et à pas fins (FBGA)

Mechanical standardization of semiconductor devices - Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device package - Design guide for fine-pitch ball grid array (FBGA) (IEC 60191-6-5:2001)

General Information

• Status: Published
• Publication Date: 31-Aug-2002
• ICS: 01.100.25 - Electrical and electronics engineering drawings
• ICS: 31.080.01 - Semiconductor devices in general
• ICS: 31.240 - Mechanical structures for electronic equipment
• Technical Committee: SS EIT - Technical Board for the electrotechnical, information technology and telecommunications fields
• Current Stage: 6060 - National Implementation/Publication (Adopted Project)
• Start Date: 01-Sep-2002
• Due Date: 01-Sep-2002
• Completion Date: 01-Sep-2002
• Ref Project: EN 60191-6-5:2001 - Mechanical standardization of semiconductor devices - Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch ball grid array (FBGA)

Overview

EN 60191-6-5:2001 (identical to IEC 60191-6-5:2001) is a mechanical standardization guide for fine-pitch ball grid array (FBGA) surface-mounted semiconductor device packages. It defines common outline drawings, datum references and dimensional rules for FBGA packages with a terminal pitch ≤ 0.80 mm and a square package body outline. The standard covers both plastic (P-FBGA) and ceramic (C-FBGA) interposer materials and aims to secure interchangeability between manufacturers.

Key topics

• Scope & definitions
  • Defines FBGA, flanged type and real chip size package body types.
  • Material designations: P-FBGA (resin substrate) and C-FBGA (ceramic substrate).
• Outline drawings and datums
  • Rules for preparing standardized outline drawings, including visible index zones, datum targets (A, B) and primary datum/seating plane.
• Dimensional groups
  • Grouped dimensions for mounting & interchangeability, mounting & gauging, automated handling, and informational use.
  • Recommended dimension tables for common terminal pitches (e = 0.80, 0.65, 0.50, 0.40 mm) and maximum matrix/terminal counts.
• Ball matrix and package geometry
  • Guidance on relationships among package body size, terminal count, matrix family and package overhang; includes normative tables for matrix families and recommended values.
• Normative references
  • Cross-references IEC 60191-6:1990 (general rules for SMD outline drawings).

Practical applications

Who uses EN 60191-6-5:2001 and why:

• Package designers - create standard-compliant FBGA outline drawings for consistent footprints and mechanical interfaces.
• PCB layout engineers - ensure correct land patterns, pad arrays and mechanical clearances for fine-pitch BGA mounting.
• Component manufacturers - design packages (P-FBGA/C-FBGA), define datums and meet interchangeability expectations.
• Assembly & test houses - align pick-and-place, soldering and automated handling equipment with standardized package dimensions and tolerances.
• Procurement/quality teams - verify vendor parts against standardized outlines to reduce footprint variants and improve supply-chain compatibility.

Practical benefits include improved interchangeability, reduced redesign risk, consistent automated handling profiles and clearer supplier/contractor specifications.

Related standards

• IEC 60191-6:1990 - General rules for the preparation of outline drawings of surface-mounted semiconductor device packages (normative reference).
• EN 60191-6-5:2001 is published by CENELEC (CLC) and mirrors IEC 60191-6-5:2001.

Keywords: EN 60191-6-5:2001, IEC 60191-6-5, FBGA, fine-pitch ball grid array, surface mounted semiconductor device packages, outline drawings, terminal pitch ≤ 0.80 mm, P-FBGA, C-FBGA, package interchangeability.

Standards Content (Sample)

2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.Mechanical standardization of semiconductor devices - Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device package - Design guide for fine-pitch ball grid array (FBGA) (IEC 60191-6-5:2001)Mechanische Normung von Halbleiterbauelemente -- Teil 6-5: Allgemeine Regeln für die Erstellung von Gehäusezeichnungen von SMD-Halbleitergehäusen - Konstruktionsleitfaden für Feinraster-Ball-Grid-Arrays (FBGA)Normalisation mécanique des dispositifs à semiconducteurs -- Partie 6-5: Règles générales pour la préparation des dessins d'encombrement des dispositifs à semiconducteurs à montage en surface - Guide de conception pour les boîtiers matriciels à billes et à pas fins (FBGA)Mechanical standardization of semiconductor devices -- Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch ball grid array (FBGA)31.240Mehanske konstrukcije za elektronsko opremoMechanical structures for electronic equipment31.080.01Polprevodniški elementi (naprave) na splošnoSemiconductor devices in general01.100.25Electrical and electronics engineering drawingsICS:Ta slovenski standard je istoveten z:EN 60191-6-5:2001SIST EN 60191-6-5:2002en01-september-2002SIST EN 60191-6-5:2002SLOVENSKI
STANDARD
EUROPEAN STANDARDEN 60191-6-5NORME EUROPÉENNEEUROPÄISCHE NORMOctober 2001CENELECEuropean Committee for Electrotechnical StandardizationComité Européen de Normalisation ElectrotechniqueEuropäisches Komitee für Elektrotechnische NormungCentral Secretariat: rue de Stassart 35, B - 1050 Brussels© 2001 CENELEC -All rights of exploitation in any form and by any means reserved worldwide for CENELEC members.Ref. No. EN 60191-6-5:2001 EICS 31.080.01English versionMechanical standardization of semiconductor devicesPart 6-5: General rules for the preparation of outline drawings ofsurface mounted semiconductor device packages -Design guide for fine-pitch ball grid array (FBGA)(IEC 60191-6-5:2001)Normalisation mécanique des dispositifsà semiconducteursPartie 6-5: Règles générales pourla préparation des dessinsd'encombrement des dispositifs àsemiconducteurs à montage en surface -Guide de conception pour les boîtiersmatriciels à billes et à pas fins (FBGA)(CEI 60191-6-5:2001)Mechanische Normung vonHalbleiterbauelementeTeil 6-5: Allgemeine Regeln fürdie Erstellung von Gehäusezeichnungenvon SMD-Halbleitergehäusen -Konstruktionsleitfaden für Feinraster-Ball-Grid-Arrays (FBGA)(IEC 60191-6-5:2001)This European Standard was approved by CENELEC on 2001-10-01. CENELEC members are bound tocomply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this EuropeanStandard the status of a national standard without any alteration.Up-to-date lists and bibliographical references concerning such national standards may be obtained onapplication to the Central Secretariat or to any CENELEC member.This European Standard exists in three official versions (English, French, German). A version in any otherlanguage made by translation under the responsibility of a CENELEC member into its own language andnotified to the Central Secretariat has the same status as the official versions.CENELEC members are the national electrotechnical committees of Austria, Belgium, Czech Republic,Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Malta, Netherlands,Norway, Portugal, Spain, Sweden, Switzerland and United Kingdom.SIST EN 60191-6-5:2002

- 3 -EN 60191-6-5:2001Annex ZA(normative)Normative references to international publicationswith their corresponding European publicationsThis European Standard incorporates by dated or undated reference, provisions from otherpublications. These normative references are cited at the appropriate places in the text and thepublications are listed hereafter. For dated references, subsequent amendments to or revisions of anyof these publications apply to this European Standard only when incorporated in it by amendment orrevision. For undated references the latest edition of the publication referred to applies (includingamendments).NOTEWhen an international publication has been modified by common modifications, indicated by (mod), the relevantEN/HD applies.PublicationYearTitleEN/HDYearIEC 60191-61990Mechanical standardization ofsemiconductor devicesPart 6: General rules for the preparationof outline drawings of surface mountedsemiconductor device packages--SIST EN 60191-6-5:2002

INTERNATIONALSTANDARDIEC60191-6-5First edition2001-08Mechanical standardizationof semiconductor devices –Part 6-5:General rules for the preparation of outlinedrawings of surface mounted semiconductordevice packages –Design guide for fine-pitch ball grid array (FBGA)Normalisation mécanique des dispositifs à semiconducteursPartie 6-5:Règles générales pour la préparation des dessinsd'encombrement des dispositifs à semiconducteursà montage en surface –Guide de conception pour les boîtiers matriciels à billeset à pas fins (FBGA)PRICE CODE IEC 2001

Copyright - all rights reservedNo part of this publication may be reproduced or utilized in any form or by any means, electronic ormechanical, including photocopying and microfilm, without permission in writing from the publisher.International Electrotechnical Commission3, rue de Varembé
Geneva, SwitzerlandTelefax: [phone]e-mail: [e-mail] IEC web site
http://www.iec.chKFor price, see current catalogue Commission Electrotechnique Internationale International Electrotechnical CommissionSIST EN 60191-6-5:2002

– 2 –60191-6-5 © IEC:2001(E)INTERNATIONAL ELECTROTECHNICAL COMMISSION–––––––––––MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES –Part 6-5: General rules for the preparation of outline drawingsof surface mounted semiconductor device packages –Design guide for fine-pitch ball grid array (FBGA)FOREWORD1)The IEC (International Electrotechnical Commission) is a worldwide organization for standardization comprisingall national electrotechnical committees (IEC National Committees). The object of the IEC is to promoteinternational co-operation on all questions concerning standardization in the electrical and electronic fields. Tothis end and in addition to other activities, the IEC publishes International Standards. Their preparation isentrusted to technical committees; any IEC National Committee interested in the subject dealt with mayparticipate in this preparatory work. International, governmental and non-governmental organizations liaisingwith the IEC also participate in this preparation. The IEC collaborates closely with the InternationalOrganization for Standardization (ISO) in accordance with conditions determined by agreement between thetwo organizations.2)The formal decisions or agreements of the IEC on technical matters express, as nearly as possible, aninternational consensus of opinion on the relevant subjects since each technical committee has representationfrom all interested National Committees.3)The documents produced have the form of recommendations for international use and are published in the formof standards, technical specifications, technical reports or guides and they are accepted by the NationalCommittees in that sense.4)In order to promote international unification, IEC National Committees undertake to apply IEC InternationalStandards transparently to the maximum extent possible in their national and regional standards. Anydivergence between the IEC Standard and the corresponding national or regional standard shall be clearlyindicated in the latter.5)The IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for anyequipment declared to be in conformity with one of its standards.6)Attention is drawn to the possibility that some of the elements of this International Standard may be the subjectof patent rights. The IEC shall not be held responsible for identifying any or all such patent rights.International Standard IEC 60191-6-5 has been prepared by subcommittee 47D: Mechanicalstandardization of semiconductor devices, of IEC technical committee 47: Semiconductordevices.The text of this standard is based on the following documents:FDISReport on voting47D/437/FDIS47D/455/RVDFull information on the voting for the approval of this standard can be found in the report onvoting indicated in the above table.Thi
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