oSIST prEN IEC 63567-4:2026

• Status: Not Published
• Public Enquiry End Date: 31-Jul-2026
• ICS: 31.080.99 - Other semiconductor devices
• Technical Committee: I11 - Imaginarni 11
• Current Stage: 4020 - Public enquire (PE) (Adopted Project)
• Start Date: 26-May-2026
• Due Date: 13-Oct-2026
• Completion Date: 03-Aug-2026
• Ref Project: prEN IEC 63567-4:2026 - Semiconductor devices - Performance evaluation of semiconductor processing components and inspection equipment - Part 4: Evaluation methods for dimensional accuracy of laser dicing process

oSIST prEN IEC 63567-4:2026 is the Slovenian standard published by SIST and identical to prEN IEC 63567-4:2026. It belongs to the IEC 63567 series on performance evaluation of semiconductor processing components and inspection equipment. This part specifies methods for evaluating the dimensional accuracy of singulated dies after laser dicing, mainly for thin silicon wafers used in semiconductor manufacturing.

What does oSIST prEN IEC 63567-4:2026 specify?

oSIST prEN IEC 63567-4:2026 specifies how to evaluate the dimensional accuracy of dies after the laser dicing process. It is written for semiconductor manufacturing and inspection work where the cut quality of singulated dies has to be measured and reported in a repeatable way.

The document is organized into clauses on scope, terms and definitions, laser dicing procedures, die preparation for test, test items for dimensional accuracy, and test report, plus two informative annexes.

Annex	What it covers
Annex A	Market relevance and the background for the need for the standard
Annex B	An example of the test report

What are the key requirements of oSIST prEN IEC 63567-4:2026?

Clause 4 follows the laser dicing flow through laser scribing, backside grinding, and die separation. In practice, this matters because the document links each measurement to a specific stage in the process, so users can compare results with the exact production step.

Clause 5 requires the test wafer to reflect the actual manufacturing process, with size, thickness, and surface properties taken into account. If relevant, bow, warp, or total thickness variation (TTV) may be recorded, which helps relate dicing results to wafer condition.

Test specimens are taken from the diced wafer and their locations are recorded. This is important because the report has to show where each measurement was made on the wafer, not just the final numbers.

Clause 6.1 evaluates straightness by comparing the desired cutting line with the actual cutting line. The setup uses a microscope, three-dimensional translational stage, and jig, with resolution below 1 μm at high magnification, so the user can measure very small cut-line deviations and report both straightness and offset.

Clause 6.2 evaluates sidewall quality through taper and sidewall flatness. The user measures edge thickness, crack shift, and the sidewall profile, which gives a practical view of whether the die wall is leaning or laterally distorted after dicing.

Clause 6.3 evaluates chipping with front-view and top-view observations. The standard requires the threshold for chipping to be stated in the test conditions and the dimensional component used for the chipping size to be identified, so the user can count individual chippings consistently and report their sizes.

Clause 7 defines the test report content. The report covers wafer specification, laser dicing process parameters, measurement conditions, and the dimensional accuracy evaluation, which makes it possible to trace a result back to the wafer, the process settings, and the measurement setup.

What terms does oSIST prEN IEC 63567-4:2026 define?

• Laser dicing - a wafer-cutting method that scans laser light along dicing lines on a substrate.
• Desired cutting line - the nominal cutting path based on alignment keys or chip patterns.
• (Actual) cutting line - the path of the outer edge of the singulated die in top view.
• Straightness - the variation of the actual cutting line from the desired cutting line.
• Taper - the angle formed by the inclination of the chip cross-section after laser dicing.
• Sidewall profile - the edge path of the singulated die seen from the side view.
• Chipping - local breakage or material loss at a die edge or surface during dicing.
• Sidewall flatness - the horizontal distance between the innermost and outermost points of the sidewall profile.

Who uses oSIST prEN IEC 63567-4:2026?

Semiconductor device manufacturers, dicing equipment suppliers, and inspection laboratories use oSIST prEN IEC 63567-4:2026 to qualify laser dicing processes and compare process settings. Quality managers and process engineers use it to document cut-line accuracy, taper, sidewall quality, and chipping in a way that can be repeated across sites or lots. Buyers and design companies can use the report structure to check whether a dicing process matches their dimensional targets and inspection expectations.

What changed in oSIST prEN IEC 63567-4:2026 from the previous edition?

oSIST prEN IEC 63567-4:2026 supersedes 47/2933/CD and 47/2972/CC.

What does the oSIST prEN IEC 63567-4:2026 document contain?

The body of the document includes the process sequence for laser dicing, the wafer and specimen preparation steps, and the measurement methods for straightness, taper, sidewall flatness, and chipping. It uses figures for the cutting-line geometry, the specimen layout, and the measurement concepts, and it uses tables for symbols and designations.

The measurement methods are set up for visual inspection equipment, including microscope-based setups and cross-sectional observation after chip separation. The report section gives the information that needs to be captured for traceability and comparison.

Annex A gives background on why laser dicing became important for thinner dies and tighter cutting requirements. Annex B shows an example report, including optical microscope (OM) and scanning electron microscope (SEM) based measurements and how values are recorded for each specimen location.

SLOVENSKI STANDARD
01-julij-2026
Polprevodniški elementi - Vrednotenje učinkovitosti komponent za obdelavo
polprevodnikov in opreme za pregledovanje - 4. del: Metode ocenjevanja
dimenzijske natančnosti laserskega razreza
Semiconductor devices - Performance evaluation of semiconductor processing
components and inspection equipment - Part 4: Evaluation methods for dimensional
accuracy of laser dicing process
Ta slovenski standard je istoveten z: prEN IEC 63567-4:2026
ICS:
31.080.99 Drugi polprevodniški elementi Other semiconductor devices
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

47/3011/CDV
COMMITTEE DRAFT FOR VOTE (CDV)
PROJECT NUMBER:
IEC 63567-4 ED1
DATE OF CIRCULATION: CLOSING DATE FOR VOTING:
2026-05-22 2026-08-14
SUPERSEDES DOCUMENTS:
47/2933/CD, 47/2972/CC
IEC TC 47 : SEMICONDUCTOR DEVICES
SECRETARIAT: SECRETARY:
Korea, Republic of Mr Cheolung Cha
OF INTEREST TO THE FOLLOWING COMMITTEES: HORIZONTAL FUNCTION(S):

ASPECTS CONCERNED:
SUBMITTED FOR CENELEC PARALLEL VOTING NOT SUBMITTED FOR CENELEC PARALLEL VOTING
Attention IEC-CENELEC parallel voting
The attention of IEC National Committees, members of
CENELEC, is drawn to the fact that this Committee Draft
for Vote (CDV) is submitted for parallel voting.
The CENELEC members are invited to vote through the
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This document is still under study and subject to change. It should not be used for reference purposes.
Recipients of this document are invited to submit, with their comments, notification of any relevant patent rights of
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Recipients of this document are invited to submit, with their comments, notification of any relevant “In Some
Countries” clauses to be included should this proposal proceed. Recipients are reminded that the CDV stage is
the final stage for submitting ISC clauses. (SEE AC/22/2007 OR NEW GUIDANCE DOC).

TITLE:
Semiconductor devices - Performance evaluation of semiconductor processing components
and inspection equipment - Part 4: Evaluation methods for dimensional accuracy of laser
dicing process
PROPOSED STABILITY DATE: 2029
NOTE FROM TC/SC OFFICERS:
download this electronic file, to make a copy and to print out the content for the sole purpose of preparing National
Committee positions. You may not copy or "mirror" the file or printed version of the document, o r any part of it,
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IEC CDV 63567-4 ED1 © IEC 2026
1 CONTENTS
2 FOREWORD . 4
3 INTRODUCTION . 5
4 1 Scope . 6
5 2 Normative references . 6
6 3 Terms and definitions . 6
7 4 Procedures of laser dicing . 7
8 4.1 Laser scribing . 7
9 4.2 Backside grinding . 7
10 4.3 Die separation . 7
11 5 Die separation for test . 7
12 5.1 Wafer selection . 7
13 5.2 Test specimen . 8
14 6 Test items for dimensional accuracy . 8
15 6.1 Straightness. 8
16 6.1.1 Measurement setup . 8
17 6.1.2 Evaluation of straightness . 8
18 5.2 Sidewall quality . 9
19 6.2.1 Measurement setup . 9
20 6.2.2 Evaluation of taper . 10
21 6.2.3 Evaluation of sidewall flatness . 10
22 6.3 Chipping . 11
23 6.3.1 Measurement setup . 11
24 6.3.2 Evaluation of chipping . 11
25 7 Test report . 12
26 7.1 Wafer specification . 12
27 7.2 Laser dicing process parameters . 12
28 7.3 Measurement conditions . 12
29 7.4 Dimensional accuracy evaluation . 12
30 Annex A (informative) Market relevance for the need of the standard . 13
31 Annex B (informative) An example for the test report . 14
32 B.1 Test specimen . 15
33 B.2 Straightness evaluation . 15
34 B.3 Taper evaluation . 15
35 B.4 Sidewall quality evaluation . 16
36 Bibliography . 17
38 Figure 1 – Schematic for typical procedures of the laser dicing process . 7
39 Figure 2 – Schematic of the test specimens in the diced wafer . 8
40 Figure 3 – Top view of desired cutting line and actual cutting line . 9
41 Figure 4 – Evaluation of straightness and offset . 9
42 Figure 5 – Evaluation of taper . 10
43 Figure 6 – Evaluation of sidewall flatness . 10
44 Figure 7 – Evaluation of chipping . 11
45 Figure A.1 – Evolution of die singulation process of silicon wafer in semiconductor
46 industry . 13
IEC CDV 63567-4 ED1 © IEC 2026
47 Figure B.1 – Test specimen location . 15
48 Figure B.2 – An optical microscope image for straightness evaluation . 15
49 Figure B.3 – A scanning electron microscope image for taper evaluation . 15
50 Figure B.4 – A scanning electron microscope image for sidewall quality evaluation . 16
IEC CDV 63567-4 ED1 © IEC 2026
52 INTERNATIONAL ELECTROTECHNICAL COMMISSION
53 ____________
55 SEMICONDUCTOR DEVICES – PERFORMANCE EVALUATION OF
56 SEMICONDUCTOR PROCESSING COMPONENTS AND INSPECTION
57 EQUIPMENT -
59 Part 4: Evaluation methods for dimensional accuracy of laser dicing
60 process
62 FOREWORD
63 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
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99 IEC 63567 has been prepared by IEC technical committee TC47: Semiconductor devices. It is
100 an International Standard.
101 The text of this International Standard is based on the following documents:
Draft Report on voting
XX/XX/FDIS XX/XX/RVD
103 Full information on the voting for its approval can be found in the report on voting indicated in
104 the above table.
IEC CDV 63567-4 ED1 © IEC 2026
105 The language used for the development of this International Standard is English.
106 This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
107 accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available
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112 specific document. At this date, the document will be
113 • reconfirmed,
114 • withdrawn, or
115 • revised.
IEC CDV 63567-4 ED1 © IEC 2026
117 INTRODUCTION
118 Recently, the semiconductor market continues to increase, and the demand and importance of
119 semiconductor modules and equipment for manufacturing semiconductor devices are also continuously
120 increasing. With the miniaturization of semiconductor manufacturing processes, the need to develop
121 new semiconductor equipment is also increasing. Therefore, it is necessary to develop an international
122 standard to evaluate the parts and modules used in semiconductor equipment. There are many
123 semiconductor processing components: wafer, mask and pellicle, etc. These components have a
124 significant impact on the performance, reliability, and manufacturing yield of semiconductor devices.
125 Therefore, it is very important to establish the international standards for evaluating or inspecting the
126 parts and modules used in semiconductor equipment.
128 IEC 63567 series of standards is planned to focus on performance evaluation of semiconductor
129 processing components and inspection equipment.
131 Part 1 focuses on the apparatus and its method for measuring the extreme ultraviolet (EUV)
132 transmission of a pellicle used in the EUV lithography process to physically prevent particle
133 contamination of the mask.
135 Part 2 deals with advanced techniques for inspecting nano-scale defects on wafers using white light
136 interferometry. Thanks to recent development of wafer inspection techniques, even smaller defects can
137 be detected by using UV light source and related optics. Part 3 describes the wafer inspection method
138 by UV light.
140 The dimensional accuracy of the silicon dies after the dicing process is becoming more important as
141 semiconductor device and packaging technologies have been advanced. Part 4 focuses on evaluation
142 methods for dimensional accuracy of singulated dies by laser dicing process. Laser dicing is one of the
143 most widely used wafer-cutting technologies in the semiconductor device manufacturing processes that
144 require high dimensional accuracy. It is essential to assess the geometric characteristics of the laser-
145 diced wafers and verify their compliance with design specifications.
147 The current structure of this International Standard is as follows.
148 Part 1: Transmittance evaluation method of EUV pellicle
149 Part 2: Nano-scale wafer surface inspection using white light interferometry
150 Part 3: Nano-scale wafer surface inspection method using UV light
151 Part 4: Evaluation methods for dimensional accuracy of laser dicing process
153 1 Scope
154 This part of IEC 63567 specifies the evaluation methods for dimensional accuracy of the
155 singulated dies after laser dicing process. This evaluation method mainly targets the laser
156 dicing process of the thin silicon wafers for semiconductor industry, but can be applied to other
157 materials or applications.
IEC CDV 63567-4 ED1 © IEC 2026
158 2 Normative references
159 There are no normative references in this document.
160 3 Terms and definitions
161 For the purposes of this document, the following terms and definitions apply.
162 ISO and IEC maintain terminological databases for use in standardization at the following
163 addresses:
164 • IEC Electropedia: available at http://www.electropedia.org/
165 • ISO Online browsing platform: available at http://www.iso.org/obp
167 3.1
168 laser dicing
169 wafer-cutting technology using a laser light that is radiated and scanned along dicing lines on
170 a substrate
171 NOTE In a cutting process where blade dicing is difficult to use, the laser dicing method is widely used where a
172 laser light is focused inside the substrate and modified layers are formed beneath the scribe lines, and finally the
173 wafer is diced by a mechanical expansion
174 [SOURCE : IEV ref 523-05-07]
175 3.2
176 desired cutting line
177 a nominal cutting path determined based on alignment keys or chip patterns. It represents the
178 intended separation boundary of the chip.
179 3.3
180 scribe line
181 path of a focused scanning laser beam in laser scribing, which is generally the same as the
182 desired cutting path if the laser equipment is calibrated accurately. As the laser beam moves
183 along the cutting path, the modified layers formed beneath the scribe line.
184 3.4
185 (actual) cutting line
186 path of the very edge on a surface of the singulated die from the top view.
187 3.5
188 straightness
189 variance of the actual cutting line from the desired cutting line through the laser dicing process
190 3.6
191 taper
192 angle between the edge of the chip pattern surface and the rear surface of the chip according
193 to the inclination angle of the cross-sectional surface observed in the chip separated after the
194 laser dicing process
195 3.7
196 sidewall profile
197 path of the very edge on a surface of the singulated die from the side view
IEC CDV 63567-4 ED1 © IEC 2026
198 3.8
199 c
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