SIST EN 61193-1:2002

Quality assessment systems -- Part 1: Registration and analysis of defects on printed board assemblies

Defines methods of registration and analysis of defects on soldered printed board assemblies. These methods are described to allow effective comparison of performance between products, processes and production locations, and can serve as a basis for general quality improvement.

Qualitätsbewertungssysteme -- Teil 1: Protokollierung und Analyse von Fehlern auf bestückten Leiterplatten

Système d'assurance de la qualité -- Partie 1: Enregistrement et analyse des défauts sur les cartes imprimées équipées

Définit les méthodes d'enregistrement et d'analyse de défauts sur les cartes imprimées équipées. Ces méthodes permettent de comparer les performances des produits, des processus et des sites de production, et peuvent servir de base pour améliorer la qualité générale.

Quality assessment systems - Part 1: Registration and analysis of defects on printed board assemblies

General Information

• Status: Published
• Publication Date: 31-Aug-2002
• ICS: 03.120.99 - Other standards related to quality
• ICS: 31.180 - Printed circuits and boards
• Technical Committee: ITIV - Electronics assembly technology and Environmental standardization
• Current Stage: 6060 - National Implementation/Publication (Adopted Project)
• Start Date: 01-Sep-2002
• Due Date: 01-Sep-2002
• Completion Date: 01-Sep-2002
• Ref Project: EN 61193-1:2002 - Quality assessment systems - Part 1: Registration and analysis of defects on printed board assemblies

Standards Content (Sample)

SLOVENSKI STANDARD
SIST EN 61193-1:2002
01-september-2002
Quality assessment systems - Part 1: Registration and analysis of defects on
printed board assemblies
Quality assessment systems -- Part 1: Registration and analysis of defects on printed
board assemblies
Qualitätsbewertungssysteme -- Teil 1: Protokollierung und Analyse von Fehlern auf
bestückten Leiterplatten
Système d'assurance de la qualité -- Partie 1: Enregistrement et analyse des défauts sur
les cartes imprimées équipées
Ta slovenski standard je istoveten z: EN 61193-1:2002
ICS:
03.120.99 Drugi standardi v zvezi s Other standards related to
kakovostjo quality
31.180 7LVNDQDYH]MD7,9LQWLVNDQH Printed circuits and boards
SORãþH
SIST EN 61193-1:2002 en
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

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SIST EN 61193-1:2002

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SIST EN 61193-1:2002
EUROPEAN STANDARD EN 61193-1
NORME EUROPÉENNE
EUROPÄISCHE NORM February 2002
ICS 31.190
English version
Quality assessment systems
Part 1: Registration and analysis of defects
on printed board assemblies
(IEC 61193-1:2001)
Système d'assurance de la qualité Qualitätsbewertungssysteme
Partie 1: Enregistrement et analyse Teil 1: Protokollierung und Analyse
des défauts sur les cartes von Fehlern auf bestückten Leiterplatten
imprimées équipées (IEC 61193-1:2001)
(CEI 61193-1:2001)
This European Standard was approved by CENELEC on 2002-02-01. CENELEC members are bound to
comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European
Standard the status of a national standard without any alteration.
Up-to-date lists and bibliographical references concerning such national standards may be obtained on
application to the Central Secretariat or to any CENELEC member.
This European Standard exists in three official versions (English, French, German). A version in any other
language made by translation under the responsibility of a CENELEC member into its own language and
notified to the Central Secretariat has the same status as the official versions.
CENELEC members are the national electrotechnical committees of Austria, Belgium, Czech Republic,
Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Malta, Netherlands,
Norway, Portugal, Spain, Sweden, Switzerland and United Kingdom.
CENELEC
European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung
Central Secretariat: rue de Stassart 35, B - 1050 Brussels
© 2002 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members.
Ref. No. EN 61193-1:2002 E

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SIST EN 61193-1:2002
EN 61193-1:2002 - 2 -
Foreword
The text of document 91/265/FDIS, future edition 1 of IEC 61193-1, prepared by IEC TC 91, Electronics
assembly technology, was submitted to the IEC-CENELEC parallel vote and was approved by
CENELEC as EN 61193-1 on 2002-02-01.
The following dates were fixed:
– latest date by which the EN has to be implemented
at national level by publication of an identical
national standard or by endorsement (dop) 2002-11-01
– latest date by which the national standards conflicting
with the EN have to be withdrawn (dow) 2005-02-01
Annexes designated "normative" are part of the body of the standard.
Annexes designated "informative" are given for information only.
In this standard, annexes A and ZA are normative and annexes B, C and D are informative.
Annex ZA has been added by CENELEC.
__________
Endorsement notice
The text of the International Standard IEC 61193-1:2001 was approved by CENELEC as a European
Standard without any modification.
__________

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SIST EN 61193-1:2002
- 3 - EN 61193-1:2001
Annex ZA
(normative)
Normative references to international publications
with their corresponding European publications
This European Standard incorporates by dated or undated reference, provisions from other
publications. These normative references are cited at the appropriate places in the text and the
publications are listed hereafter. For dated references, subsequent amendments to or revisions of any
of these publications apply to this European Standard only when incorporated in it by amendment or
revision. For undated references the latest edition of the publication referred to applies (including
amendments).
NOTE When an international publication has been modified by common modifications, indicated by (mod), the relevant
EN/HD applies.
Publication Year Title EN/HD Year
1)
IEC 60194 - Printed board design, manufacture and--
assembly - Terms and definitions
1) 2)
IEC 61191-1 - Printed board assemblies EN 61191-1 1998
Part 1: Generic specification –
Requirements for soldered electrical
and electronic assemblies using surface
mount and related assembly
technologies
1) 2)
IEC 61191-2 - Part 2: Sectional specification – EN 61191-2 1998
Requirements for surface mount
soldered assemblies
1) 2)
IEC 61191-3 - Part 3: Sectional specification – EN 61191-3 1998
Requirements for through-hole mount
soldered assemblies
1) 2)
IEC 61191-4 - Part 4: Sectional specification – EN 61191-4 1998
Requirements for terminal soldered
assemblies
3)
IEC 61192-1 - Product performance requirements--
Part 1: Generic standard - Workmanship
requirements for soldered electronic
assemblies
3)
IEC 61192-2 - Part 2: Sectional standard - --
Workmanship requirements for surface
mount soldered electronic assemblies
3)
IEC 61192-3 - Part 3: Sectional standard - --
Workmanship requirements for through-
hole mount soldered assemblies

1)
Undated reference.
2)
Valid edition at time of issue.
3)
To be published.

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SIST EN 61193-1:2002
EN 61193-1:2002 - 4 -
Publication Year Title EN/HD Year
3)
IEC 61192-4 - Part 4: Sectional standard - --
Workmanship requirements for terminal
soldered assemblies

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SIST EN 61193-1:2002

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SIST EN 61193-1:2002
NORME
CEI
INTERNATIONALE IEC
61193-1
INTERNATIONAL
Première édition
STANDARD
First edition
2001-12
Système d'assurance de la qualité –
Partie 1:
Enregistrement et analyse des défauts
sur les cartes imprimées équipées
Quality assessment systems –
Part 1:
Registration and analysis of defects
on printed board assemblies
© IEC 2001 Droits de reproduction réservés ⎯ Copyright - all rights reserved
Aucune partie de cette publication ne peut être reproduite ni No part of this publication may be reproduced or utilized in
utilisée sous quelque forme que ce soit et par aucun procédé, any form or by any means, electronic or mechanical,
électronique ou mécanique, y compris la photocopie et les including photocopying and microfilm, without permission in
microfilms, sans l'accord écrit de l'éditeur. writing from the publisher.
International Electrotechnical Commission 3, rue de Varembé Geneva, Switzerland
Telefax: [phone] e-mail: [e-mail] IEC web site http://www.iec.ch
CODE PRIX
Commission Electrotechnique Internationale
S
PRICE CODE
International Electrotechnical Commission
Pour prix, voir catalogue en vigueur
For price, see current catalogue

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SIST EN 61193-1:2002
61193-1 © IEC:2001 – 3 –
CONTENTS
FOREWORD.5
INTRODUCTION.9
1 Scope.11
2 Normative references .11
3 Terms and definitions .13
4 Defect registration .19
4.1 Accept criteria .19
4.2 Counting of defects .19
4.3 Post-soldering defect registration .21
4.3.1 Defects found after testing.21
4.4 Defect subdivision .21
4.4.1 Defect sources .21
4.4.2 Defect registration form .21
4.5 Rework immediately prior to soldering .23
4.6 Defect data categories .23
5 Processing the data.23
6 Analysis.25
Annex A (normative)  Subprocesses .27
Annex B (informative)  Examples of product defect qualification .29
Annex C (informative) Examples of calculations.33
Annex D (informative)  Example of registration of defects and processing of the data .37
Figure B.1 – Registration of defects .31
Figure D.1 – Data for defect registration .37
Figure D.2 – Subdivision into type of defect .39
Figure D.3 – Subdivision into type of component.39
Figure D.4 – Subdivision into defect source .39
Figure D.5 – ppm level printed board A, of the past 10 production days .41
Figure D.6 – ppm levels of the production per type of board.41
Table A.1 – Descriptions for subprocesses .27
Table C.1 – Example 1 (100 % check) .33
Table C.2 – Example 2 (random check) .35
Table D.1 – Three subdivisions.39

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SIST EN 61193-1:2002
61193-1 © IEC:2001 – 5 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
QUALITY ASSESSMENT SYSTEMS –
Part 1: Registration and analysis of defects
on printed board assemblies
FOREWORD
1) The IEC (International Electrotechnical Commission) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of the IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, the IEC publishes International Standards. Their preparation is
entrusted to technical committees; any IEC National Committee interested in the subject dealt with may
participate in this preparatory work. International, governmental and non-governmental organizations liaising
with the IEC also participate in this preparation. The IEC collaborates closely with the International
Organization for Standardization (ISO) in accordance with conditions determined by agreement between the
two organizations.
2) The formal decisions or agreements of the IEC on technical matters express, as nearly as possible, an
international consensus of opinion on the relevant subjects since each technical committee has representation
from all interested National Committees.
3) The documents produced have the form of recommendations for international use and are published in the form
of standards, technical specifications, technical reports or guides and they are accepted by the National
Committees in that sense.
4) In order to promote international unification, IEC National Committees undertake to apply IEC International
Standards transparently to the maximum extent possible in their national and regional standards. Any
divergence between the IEC Standard and the corresponding national or regional standard shall be clearly
indicated in the latter.
5) The IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with one of its standards.
6) Attention is drawn to the possibility that some of the elements of this International Standard may be the subject
of patent rights. The IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 61193-1 has been prepared by IEC technical committee 91:
Electronics assembly technology.
The text of this standard is based on the following documents:
FDIS Report on voting
91/265/FDIS 91/273/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 3.
Annex A forms an integral part of this standard.
Annexes B, C and D are for information only.

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SIST EN 61193-1:2002
61193-1 © IEC:2001 – 7 –
The committee has decided that the contents of this publication will remain unchanged
until 2006. At this date, the publication will be
• reconfirmed;
• withdrawn;
• replaced by a revised edition, or
• amended.

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SIST EN 61193-1:2002
61193-1 © IEC:2001 – 9 –
INTRODUCTION
This part of IEC 61193 enables the counting of defects on soldered printed board assemblies
in the manufacture of electronic circuits and the associated calculation of ppm (parts per
million) data to be carried out in a standard manner.
The number of defects occurring during the production process is usually expressed at lower
defect levels in parts per million, commonly indicated as ppm. On the face of it, the meaning
of the ppm value of a soldering process is self-evident: a part is, in this context, a soldered
joint that is defective, the million refers to a million soldered joints.
For a uniform registration of defects it is emphasized that in this standard the soldering
defects are counted immediately after the actual soldering operation (on emergence of the
soldered assembly from the soldering machine). By the Pareto analysis method it can be
assessed whether the defect should be attributed to the soldering process proper or to
another cause.
In order to manage the ppm values to be calculated, there is a need to understand the
mathematical significance of the number of defects found in a batch of a particular size (i.e.
smaller than the size of the entire lot of products) and its consequences for the entire lot.
Mentioning the ppm value of a certain soldering process, without reference to the number of
soldered joints and without giving the level of confidence is of little use.
For making ppm calculations, several methods are described by which the maximum ppm
level to be expected can be determined, for example:
– by using the formula that describes the binomial distribution to construct this distribution;
– by using graphs or tables from the literature.

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SIST EN 61193-1:2002
61193-1 © IEC:2001 – 11 –
QUALITY ASSESSMENT SYSTEMS –
Part 1: Registration and analysis of defects
on printed board assemblies
1 Scope
This part of IEC 61193 defines methods of registration and analysis of defects on soldered
printed board assemblies. Methods are described to allow effective comparison of perform-
ance between products, processes and production locations and can serve as a basis for
general quality improvement.
The standard specifies defect data collection in two categories.
Category 1 ppm data: this category provides data for registration purposes intended to enable
overall performance comparison of assembly operations.
Category 2 ppm data: this category provides data intended for individual subprocess
assessment, analysis and control purposes.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
IEC 60194, Printed board design, manufacture and assembly – Terms and definitions
IEC 61191-1, Printed board assemblies – Part 1: Generic specification – Requirements for
soldered electrical and electronic assemblies using surface mount and related assembly
technologies
IEC 61191-2, Printed board assemblies – Part 2: Sectional specification – Requirements for
surface mount soldered assemblies
IEC 61191-3, Printed board assemblies – Part 3: Sectional specification – Requirements for
through-hole mount soldered assemblies
IEC 61191-4, Printed board assemblies – Part 4: Sectional specification – Requirements for
terminal soldered assemblies
IEC 61192-1, Product performance requirements – Part 1: Generic standard – Workmanship
1
requirements and guidelines for soldered electronic assemblies
IEC 61192-2, Product performance requirements – Part 2: Sectional standard – Workmanship
1
requirements and guidelines for soldered surface mount electronic assemblies
___________
1
 To be published.

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SIST EN 61193-1:2002
61193-1 © IEC:2001 – 13 –
IEC 61192-3, Product performance requirements – Part 3: Sectional standard – Workmanship
2
requirements for through-hole mount soldered assemblies
IEC 61192-4, Product performance requirements – Part 4: Sectional standard – Workmanship
2
requirements for terminal soldered connections
3 Terms and definitions
3
For the purposes of this part of IEC 61193 the definitions in IEC 60194 and the following
apply. Where appropriate, an alpha-numerical code has been assigned to the term in order to
assist the registration and disposition of defects or process deviation indicators.
3.1
general characterizations
conditions or attributes of the final electronic assembly that may be compared to the require-
ments of the appropriate documentation or performance specification
3.1.1
defect registration
uniform registration system for collecting information on electronic assembly attributes that
can be accredited to a subprocess or a final product configuration, made before any touch-up
or repair process
3.1.2
subprocesses
major manufacturing functions used to produce electronic assemblies that are an integral part
of the manufacturing process to which process deviation indicators or defects defining non-
conforming attributes may be assigned
3.1.3
printed board solder joint
electrical/mechanical connection to a printed board or other interconnecting structure that
employs solder for the joining of two or more metal surfaces
NOTE  See also the definitions of cold soldered connection, disturbed soldered connection, excess soldered
connection, insufficient soldered connection, overheated soldered connection, preferred soldered connection and
rosin soldered connection in IEC 60194.
3.2
solder paste application (P0)
subprocess used to apply solder paste to a land pattern on a printed board or interconnecting
structure for the purpose of attaching components using solder reflow techniques
3.2.1
paste misalignment (P1)
image of solder paste geometric profiles positioned so that they are not registered to the land
pattern on the printed board/interconnecting structure used to mount components
___________
2
 To be published.
3
 Certain definitions of IEC 60194 have been translated into French.

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SIST EN 61193-1:2002
61193-1 © IEC:2001 – 15 –
3.2.2
excessive paste (P2)
solder paste geometric profiles that consist of greater paste volume than that defined by the
assembly process details
3.2.3
insufficient/no paste (P3)
solder paste geometric profiles that consist of less paste volume than that defined by the
assembly process details
3.2.4
paste smearing (P4)
solder paste application that results in the paste being spread over the mounting surface in an
uncontrolled manner rather than having a neat and well-defined geometric profile
3.2.5
paste bridging (P5)
solder paste geometric profiles that are touching or have merged across more than one
conductive pattern
3.2.6
paste deposit shape (P6)
specific solder paste geometric profile located on the printed board mounting surface as
determined by forcing the solder paste through the stencil opening
3.3
adhesive application (A0)
s
...