SIST EN 60191-6:2010

Mechanical standardization of semiconductor devices -- Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages (IEC 60191-6:2009)

IEC 60191-6:2009 gives general rules for the preparation of outline drawings of surface-mounted semiconductor devices. It supplements IEC 60191-1 and IEC 60191-3. It covers all surface-mounted devices discrete semiconductors with lead count of greater or equal to 8, as well as integrated circuits classified as form E in Clause 3 of IEC 60191-4. This third edition of IEC 60191-6 cancels and replaces the second edition, published in 2004 and constitutes a technical revision. This edition includes the following significant changes with respect to the previous edition:  a) scope is modified to cover all surface-mounted devices discrete semiconductors with lead count of greater or equal to 8;   b) editorial modifications on several pages; and    c) technical revision to ball grid array package (BGA) especially its geometrical drawing format. (two types of BGA would unify as one type as a result of revising drawing format.

Mechanische Normung von Halbleiterbauelementen - Teil 6: Allgemeine Regeln für die Erstellung von Gehäusezeichnungen von SMD-Halbleitergehäusen (IEC 60191-6:2009)

Normalisation mécanique des dispositifs à semi-conducteurs - Partie 6: Règles générales pour la préparation des dessins d'encombrement des boîtiers pour dispositifs à semi-conducteurs pour montage en surface (CEI 60191-6:2009)

La CEI 60191-6:2009 donne les règles générales pour la préparation des dessins d'encombrement des dispositifs à semi-conducteurs pour montage en surface. Elle complète la CEI 60191-1 et la CEI 60191-3. Elle couvre tous les dispositifs pour montage en surface à semi-conducteurs discrets dotés d'au moins 8 sorties, ainsi que les circuits intégrés classés 'de forme E' dans l'Article 3 de la CEI 60191-4. Cette troisième édition de la CEI 60191-6 annule et remplace la deuxième édition parue en 2004 dont elle constitue une révision technique. La présente édition contient les modifications majeures suivantes par rapport à l'édition précédente:  a) le domaine d'application est modifié pour couvrir tous les dispositifs pour montage en surface à semi-conducteurs discrets dotés d'au moins 8 sorties;   b) des modifications éditoriales sur plusieurs pages; et   c) une révision technique du boîtier matriciel à billes (BGA) particulièrement son format de dessin géométrique. (la révision du format de dessin permettrait d'unifier deux types de boîtier BGA pour n'avoir qu'un seul type.)

Standardizacija mehanskih lastnosti polprevodniških elementov - 6. del: Splošna pravila za pripravo tehničnih risb okrovov površinsko nameščenih polprevodniških elementov (IEC 60191-6:2009)

Ta del IEC 60191 podaja splošna pravila za pripravo tehničnih risb površinsko nameščenih polprevodniških elementov. Dopolnjuje IEC 60191-1 in IEC 60191-3. Zajema vse površinsko nameščene ločene polprevodniške elemente s stopnjo svinca vsaj 8 in integrirana vezja, opredeljena kot oblika E v Klavzuli 3 IEC 60191-4.

General Information

• Status: Published
• Publication Date: 18-Jan-2010
• ICS: 01.100.25 - Electrical and electronics engineering drawings
• ICS: 31.080.01 - Semiconductor devices in general
• ICS: 31.240 - Mechanical structures for electronic equipment
• Technical Committee: I11 - Imaginarni 11
• Current Stage: 6060 - National Implementation/Publication (Adopted Project)
• Start Date: 30-Dec-2009
• Due Date: 06-Mar-2010
• Completion Date: 19-Jan-2010
• Ref Project: EN 60191-6:2009 - Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages

Relations

• Replaces: SIST EN 60191-6:2005 - Mechanical standardization of semiconductor devices -- Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages
• Effective Date: 01-Mar-2010
• Revised: SIST EN 60191-6:2005 - Mechanical standardization of semiconductor devices -- Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages
• Effective Date: 04-Dec-2012

Standards Content (Sample)

SLOVENSKI STANDARD
01-marec-2010
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SIST EN 60191-6:2005
6WDQGDUGL]DFLMDPHKDQVNLKODVWQRVWLSROSUHYRGQLãNLKHOHPHQWRYGHO6SORãQD
SUDYLOD]DSULSUDYRWHKQLþQLKULVERNURYRYSRYUãLQVNRQDPHãþHQLK
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Mechanical standardization of semiconductor devices -- Part 6: General rules for the
preparation of outline drawings of surface mounted semiconductor device packages (IEC
60191-6:2009)
Mechanische Normung von Halbleiterbauelementen - Teil 6: Allgemeine Regeln für die
Erstellung von Gehäusezeichnungen von SMD-Halbleitergehäusen (IEC 60191-6:2009)
Normalisation mécanique des dispositifs à semi-conducteurs - Partie 6: Règles
générales pour la préparation des dessins d'encombrement des boîtiers pour dispositifs
à semi-conducteurs pour montage en surface (CEI 60191-6:2009)
Ta slovenski standard je istoveten z: EN 60191-6:2009
ICS:
01.100.25 5LVEHVSRGURþMD Electrical and electronics
HOHNWURWHKQLNHLQHOHNWURQLNH engineering drawings
31.080.01 Polprevodniški elementi Semiconductor devices in
(naprave) na splošno general
31.240 Mehanske konstrukcije za Mechanical structures for
elektronsko opremo electronic equipment
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

EUROPEAN STANDARD
EN 60191-6
NORME EUROPÉENNE
December 2009
EUROPÄISCHE NORM
ICS 31.080.01 Supersedes EN 60191-6:2004

English version
Mechanical standardization of semiconductor devices -
Part 6: General rules for the preparation of outline drawings of surface
mounted semiconductor device packages
(IEC 60191-6:2009)
Normalisation mécanique des dispositifs  Mechanische Normung
à semi-conducteurs - von Halbleiterbauelementen -
Partie 6: Règles générales Teil 6: Allgemeine Regeln
pour la préparation des dessins für die Erstellung
d'encombrement des boîtiers von Gehäusezeichnungen
pour dispositifs à semi-conducteurs von SMD-Halbleitergehäusen
pour montage en surface (IEC 60191-6:2009)
(CEI 60191-6:2009)
This European Standard was approved by CENELEC on 2009-12-01. CENELEC members are bound to comply
with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard
the status of a national standard without any alteration.

Up-to-date lists and bibliographical references concerning such national standards may be obtained on
application to the Central Secretariat or to any CENELEC member.

This European Standard exists in three official versions (English, French, German). A version in any other
language made by translation under the responsibility of a CENELEC member into its own language and notified
to the Central Secretariat has the same status as the official versions.

CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Cyprus, the
Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia,
Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain,
Sweden, Switzerland and the United Kingdom.

CENELEC
European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung

Central Secretariat: Avenue Marnix 17, B - 1000 Brussels

© 2009 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members.
Ref. No. EN 60191-6:2009 E
Foreword
The text of document 47D/736/CDV, future edition 3 of IEC 60191-6, prepared by SC 47D, Mechanical
standardization for semiconductor devices, of IEC TC 47, Semiconductor devices, was submitted to the
IEC-CENELEC parallel vote and was approved by CENELEC as EN 60191-6 on 2009-12-01.
This European Standard supersedes EN 60191-6:2004.
− scope is modified to cover all surface-mounted devices discrete semiconductors with lead count of
greater or equal to 8;
− editorial modifications on several pages; and
− technical revision to ball grid array package (BGA) especially its geometrical drawing format. (two
types of BGA would unify as one type as a result of revising drawing format.)
The following dates were fixed:
– latest date by which the EN has to be implemented
at national level by publication of an identical
(dop) 2010-09-01
national standard or by endorsement
– latest date by which the national standards conflicting
(dow) 2012-12-01
with the EN have to be withdrawn
Annex ZA has been added by CENELEC.
__________
Endorsement notice
The text of the International Standard IEC 60191-6:2009 was approved by CENELEC as a European
Standard without any modification.
In the official version, for Bibliography, the following notes have to be added for the standards indicated:
IEC 60191-3 NOTE  Harmonized as EN 60191-3:1999 (not modified).
ISO 2692 NOTE  Harmonized as EN ISO 2692:2006 (not modified).
__________
- 3 - EN 60191-6:2009
Annex ZA
(normative)
Normative references to international publications
with their corresponding European publications

The following referenced documents are indispensable for the application of this document. For dated
references, only the edition cited applies. For undated references, the latest edition of the referenced
document (including any amendments) applies.

NOTE  When an international publication has been modified by common modifications, indicated by (mod), the relevant EN/HD
applies.
Publication Year Title EN/HD Year

IEC 60191-1 2007 Mechanical standardization of semiconductor EN 60191-1 2007
devices -
Part 1: General rules for the preparation of
outline drawings of discrete devices

IEC 60191-4 1999 Mechanical standardization of semiconductor EN 60191-4 1999
A1 2001 devices - A1 2002
A2 2002 Part 4: Coding system and classification into A2 2002
forms of package outlines for semiconductor
device packages
ISO 1101 2004 Geometrical Product Specifications (GPS) - EN ISO 1101 2005
Geometrical tolerancing - Tolerances of form,
orientation, location and run-out

IEC 60191-6 ®
Edition 3.0 2009-11
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Mechanical standardization of semiconductor devices –
Part 6: General rules for the preparation of outline drawings of surface mounted
semiconductor device packages
Normalisation mécanique des dispositifs à semi-conducteurs –
Partie 6: Règles générales pour la préparation des dessins d'encombrement des
boîtiers pour dispositifs à semi-conducteurs pour montage en surface

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
W
CODE PRIX
ICS 31.080.01 ISBN 2-8318-1069-6
– 2 – 60191-6 © IEC:2009
CONTENTS
FOREWORD.4
1 Scope.6
2 Normative references .6
3 Terms and definitions .6
4 Design rules .7
5 Dimensions to be specified.8
6 Notes .8
Annex A (informative) Illustration of the rules.12
Annex B (informative) Optional table format.36
Bibliography.38

Figure A.1 – Illustrations of terminal projection zone.13
Figure A.2 – Isometric view of an example of gauge .13
Figure A.3a – Top view .14
Figure A.3b – Side view .14
Figure A.3c – Lead section .14
Figure A.3d – Lead side view.14
Figure A.4 – Pattern of terminal position areas .14
Figure A.5a – Top view .17
Figure A.5b – Side view .17
Figure A.5c – Lead section .17
Figure A.5d – Lead side view.17
Figure A.6 – Pattern of terminal position areas .17
Figure A.7a – Top view .20
Figure A.7b – Side view .20
Figure A.7c – Lead section .20
Figure A.7d – Lead side view.20
Figure A.8 – Pattern of terminal position areas .20
Figure A.9a – Top view .23
Figure A.9b – Side view .23
Figure A.9c – Side view .23
Figure A.9d – Lead shape.23
Figure A.9e – Lead side view.23
Figure A.9f – Lead section .23
Figure A.10 – Pattern of terminal position areas .23
Figure A.11a – Top view .26
Figure A.11b – Side view .26
Figure A.11c – Side view .26
Figure A.11d – Lead section .27
Figure A.11e – Lead shape .27
Figure A.11f – Lead side view.27

60191-6 © IEC:2009 – 3 –
Figure A.12 – Pattern of terminal position areas .27
Figure A.13a – Top View.30
Figure A.13b – Side View.30
Figure A.13c – Bottom view .30
Figure A.14 – Pattern of terminal position areas .30
Figure A.15a – Top view .33
Figure A.15b – Side view .33
Figure A.15c – Bottom view .33
Figure A.16 – Pattern of terminal position areas .33

Table 1 – Dimensions to be specified for Group 1 .9
Table 2 – Dimensions to be specified for Group 2 .10

– 4 – 60191-6 © IEC:2009
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
MECHANICAL STANDARDIZATION
OF SEMICONDUCTOR DEVICES –
Part 6: General rules for the preparation of outline drawings
of surface mounted semiconductor device packages

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC
Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and non-
governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely
with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
the latter.
5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any
services carried out by independent certification bodies.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60191-6 has been prepared by subcommittee 47D: Mechanical
standardization of semiconductor devices, of IEC technical committee 47: Semiconductor
devices.
This third edition of IEC 60191-6 cancels and replaces the second edition, published in 2004
and constitutes a technical revision. This edition includes the following significant changes
with respect to the previous edition:
a) scope is modified to cover all surface-mounted devices discrete semiconductors with lead
count of greater or equal to 8;
b) editorial modifications on several pages; and
c) technical revision to ball grid array package (BGA) especially its geometrical drawing
format. (two types of BGA would unify as one type as a result of revising drawing format.)

60191-6 © IEC:2009 – 5 –
The text of this standard is based on the following documents:
CDV Report on voting
47D/736/CDV 47D/749/RVC
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts of IEC 60191 series under the general title Mechanical standardization of
semiconductor devices can be found on the IEC website.
The committee has decided that the contents of this amendment and the base publication will
remain unchanged until the maintenance result date indicated on the IEC web site under
"http://webstore.iec.ch" in the data related to the specific publication. At this date, the
publication will be
• reconfirmed;
• withdrawn;
• replaced by a revised edition, or
• amended.
– 6 – 60191-6 © IEC:2009
MECHANICAL STANDARDIZATION
OF SEMICONDUCTOR DEVICES –
Part 6: General rules for the preparation of outline drawings
of surface mounted semiconductor device packages

1 Scope
This part of IEC 60191 gives general rules for the preparation of outline drawings of surface-
mounted semiconductor devices. It supplements IEC 60191-1 and IEC 60191-3. It covers all
surface-mounted devices discrete semiconductors with lead count of greater or equal to 8, as
well as integrated circuits classified as form E in Clause 3 of IEC 60191-4.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
IEC 60191-1:2007, Mechanical standardization of semiconductor devices – Part 1: General rules
for the preparation of outline drawings of discrete devices
IEC 60191-4:2002, Mechanical standardization of semiconductor devices – Part 4: Coding
system and classification into forms of package outlines for semiconductor device packages
ISO 1101:2004 Geometrical Product Specifications (GPS) – Geometrical tolerancing –
Tolerances of form, orientation, location and run-out
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
3.1
seating plane
plane which designates the plane of contact of the package, including any stand-off, with the
surface on which it will be mounted
NOTE This plane is often used as the reference plane.
3.2
reference plane
plane parallel to the seating plane at a distance A3 above seating plane (does not apply to
leadless package)
NOTE 1 The distance A3 is known as the reference plane distance. It determines the terminal projection zone
(see Figure 1).
NOTE 2 This distance is a theoretical dimension which is not related to any feature of the package. Its value is
chosen for each package so the length of terminal projection zone L is a good approximation of the terminal
p
length used for mounting, e.g. the length of the part of the terminal that is soldered to the substrate.

60191-6 © IEC:2009 – 7 –
3.3
terminal position area
maximum area on the seating plane within which the terminal projection zone is located,
taking into account the maximum values of L and b
p p
NOTE 1 The surface of the terminal position area is equal to l × b with, generally
1 3
l = L max. + (HDmax. – HDmin.)/2
p
= L max. + (HEmax. – HEmin.)/2
p
and b = b max. + x
p
NOTE 2 Checking can be carried out by means of an appropriate gauge (see Figure 2)
3.4
pattern of terminal position areas
group of all terminal position areas of a leaded package or folded lead package in the seating
plane
NOTE 1 For a leadless package, it is the projection of its metallized pads or terminals on the seating plane.
NOTE 2 The true positions of the centres of the terminal position areas are located on a grid with a modulus
e / e  or    e / e
D E
NOTE 3 The pattern of terminal position areas does not include tolerances stemming from mounting substrates
(printed board) design and placement machine accuracy.
3.5
coplanarity of terminals
profile tolerance controlling the location of the crowns of the bottom terminals with respect to
the seating plane
NOTE In all the other cases, the requirement for coplanarity of terminals is clarified by a note.
3.6
datum
geometrical established planes for controlling the tolerance zone
NOTE Datum S should be established by seating plane.
4 Design rules
The outline drawing of a surface-mounted semiconductor device package shall comprise in
the given sequence:
– the drawing (strictly speaking);
– the tables of dimensions;
– the notes to the tables and the drawings;
– the codification.
The drawing shall conform with the general rules for drawings laid down in IEC 60191-1,
Clause 4 and Clause 5, as well as with the specific definitions of Clause 3 above.
The following, Clause 5 and Clause 6 give, respectively, the tables of dimensions to be
specified and the notes to be called, where relevant. Supplementary dimensions and notes
may be added when required.
– 8 – 60191-6 © IEC:2009
The codification of package outlines shall be in accordance with IEC 60191-4.
5 Dimensions to be specified
Crosses in the Table 1 and Table 2 indicate where values have to be specified. In the
auxiliary right-hand column, a code indicates for which outline families each dimension is
generally relevant, as follows:
L: leaded packages packages with gull-wing leads for example; QFP, SOP,TSOP
F: folded lead packages packages with J-bent leads for example; QFJ, SOJ
P: leadless packages packages with no leads for example; QFN
B: ball grid array packages packages with ball leads for example; BGA
6 Notes
Notes referred to in the tables and in the drawings appear after Table 2; in the auxiliary right-
hand column, a code indicates for which outline families each note is generally relevant (with
the same code as in Clause 5 above).
For each particular outline package or package family, the applicable notes shall be
numbered sequentially from 1 in the order they are in the tables and then on the drawing.

60191-6 © IEC:2009 – 9 –
Table 1 – Dimensions to be specified for Group 1

Group 1 includes dimensions and numerals associated with
mounting of packages and kinds of packages. The
dimensions and numerals belonging to the group mean
values guaranteed to users and imply that mechanical

compatibility of mounting of packages can be recognized.
Concerned
family
Ref. Min. Nom. Max. Notes
n - x - 2 LFPB
nD - x - 3 LFP
nE - x - 3 LFP
A - - x LFPB
A1 x - x LFB
A2 - x - LF
A3 - - 4 LF
x(∗)
bp x - x 4 LFP
∅bp x [x] x 4 B
∅b x - x 4 B
C x - x LF
D x x x 4 LFPB
E x x x 4 LF
...