IEC 60749-26:2013

Semiconductor devices - Mechanical and climatic test methods - Part 26: Electrostatic discharge (ESD) sensitivity testing - Human body model (HBM)

IEC 60749-26:2013 establishes the procedure for testing, evaluating, and classifying components and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD). The purpose (objective) of this standard is to establish a test method that will replicate HBM failures and provide reliable, repeatable HBM ESD test results from tester to tester, regardless of component type. Repeatable data will allow accurate classifications and comparisons of HBM ESD sensitivity levels. ESD testing of semiconductor devices is selected from this test method, the machine model (MM) test method (see IEC 60749-27) or other ESD test methods in the IEC 60749 series. The HBM and MM test methods produce similar but not identical results; unless otherwise specified, this test method is the one selected. This edition includes the following significant technical changes with respect to the previous edition:
a) descriptions of oscilloscope and current transducers have been refined and updated;
b) the HBM circuit schematic and description have been improved;
c) the description of stress test equipment qualification and verification has been completely re-written;
d) qualification and verification of test fixture boards has been revised;
e) a new section on the determination of ringing in the current waveform has been added;
f) some alternate pin combinations have been included;
g) allowance for non-supply pins to stress to a limited number of supply pin groups (associated non-supply pins) and allowance for non-supply to non-supply (i.e., I/O to I/O) stress to be limited to a finite number of 2 pin pairs (coupled non-supply pin pairs);
h) explicit allowance for HBM stress using 2 pin HBM testers for die only shorted supply groups.

Dispositifs à semiconducteurs - Méthodes d'essais mécaniques et climatiques - Partie 26: Essai de sensibilité aux décharges électrostatiques (DES) - Modèle du corps humain (HBM)

La CEI 60749-26:2013 établit une procédure pour les essais, l'évaluation et la classification des composants et des microcircuits en fonction de leur susceptibilité (sensibilité) aux dommages ou de leur dégradation suite à leur exposition à des décharges électrostatiques (DES) sur un modèle de corps humain (HBM) défini. Le but (objectif) de cette norme est de déterminer une méthode d'essai permettant de reproduire les défaillances du HBM et de fournir des résultats d'essais de DES de HBM fiables et reproductibles d'un appareil d'essai à un autre, sans tenir compte du type de composant. Des données reproductibles autoriseront des classifications et des comparaisons précises des niveaux de sensibilité de DES de HBM. Les essais de DES des dispositifs à semiconducteurs sont choisis entre la présente méthode d'essai, celle du modèle de machine (MM) (voir CEI 60749-27) ou toute autre méthode d'essai de la série CEI 60749. Les méthodes d'essai HBM et MM produisent des résultats similaires mais non identiques; sauf indication contraire, la présente méthode d'essai est celle qui prévaut. Cette édition inclut les modifications techniques majeures suivantes par rapport à l'édition précédente:
a) les descriptions de l'oscilloscope et des transducteurs de courant ont été améliorées et mises à jour;
b) le schéma de circuit et la description du HBM ont été améliorés;
c) la description de la qualification et de la vérification du matériel d'essai de contrainte a été entièrement réécrite;
d) la qualification et la vérification des cartes de montage d'essai ont été révisées;
e) une nouvelle section concernant la détermination de l'oscillation de la forme d'onde de courant a été ajoutée;
f) certaines variantes de combinaisons de broches ont été incluses;
g) autorisation de contrainte pour les broches n'assurant pas l'alimentation jusqu'à un nombre limité de groupes de broches d'alimentation (broches associées n'assurant pas l'alimentation) et autorisation de limiter les contraintes entre broches n'assurant pas l'alimentation et broches n'assurant pas l'alimentation (c'est-à-dire, E/S vers E/S) à un nombre fini de 2 paires de broches (paires de broches couplées n'assurant pas l'alimentation);
- h) autorisation explicite de contrainte de HBM utilisant des appareils d'essai de HBM à 2 broches pour puce seulement pour des groupes d'alimentations court-circuitées.

General Information

• Status: Published
• Publication Date: 22-Apr-2013
• ICS: 31.080.01 - Semiconductor devices in general
• ICS: 33.200 - Telecontrol. Telemetering
• ICS: 35.100 - Open systems interconnection (OSI)
• Technical Committee: TC 47 - Semiconductor devices
• Drafting Committee: WG 2 - TC 47/WG 2
• Current Stage: DELPUB - Deleted Publication
• Start Date: 31-Jan-2017
• Completion Date: 15-Jan-2018

Relations

• Revised: IEC 60749-26:2018 - Semiconductor devices - Mechanical and climatic test methods - Part 26: Electrostatic discharge (ESD) sensitivity testing - Human body model (HBM)
• Effective Date: 05-Sep-2023

Standards Content (Sample)

IEC 60749-26


®


Edition 3.0 2013-04



INTERNATIONAL



STANDARD



NORME
INTERNATIONALE
colour
inside


Semiconductor devices – Mechanical and climatic test methods –
Part 26: Electrostatic discharge (ESD) sensitivity testing – Human body model
(HBM)

Dispositifs à semiconducteurs – Méthodes d'essais mécaniques et climatiques –
Partie 26: Essai de sensibilité aux décharges électrostatiques (DES) – Modèle du
corps humain (HBM)


IEC 60749-26:2013

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IEC 60749-26



®



Edition 3.0 2013-04







INTERNATIONAL





STANDARD







NORME



INTERNATIONALE
colour

inside










Semiconductor devices – Mechanical and climatic test methods –

Part 26: Electrostatic discharge (ESD) sensitivity testing – Human body model

(HBM)




Dispositifs à semiconducteurs – Méthodes d'essais mécaniques et climatiques –

Partie 26: Essai de sensibilité aux décharges électrostatiques (DES) – Modèle du


corps humain (HBM)














INTERNATIONAL

ELECTROTECHNICAL

COMMISSION


COMMISSION

ELECTROTECHNIQUE

PRICE CODE
INTERNATIONALE

CODE PRIX X


ICS 31.080.01 ISBN 978-2-83220-746-8



Warning! Make sure that you obtained this publication from an authorized distributor.

Attention! Veuillez vous assurer que vous avez obtenu cette publication via un distributeur agréé.

® Registered trademark of the International Electrotechnical Commission
Marque déposée de la Commission Electrotechnique Internationale

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CONTENTS


FOREWORD . 4

1 Scope . 6


2 Normative references . 6

3 Terms and definitions . 6

4 Apparatus and required equipment . 9

4.1 Waveform verification equipment . 9

4.2 Oscilloscope . 10

4.3 Additional requirements for digital oscilloscopes . 10
4.4 Current transducer (inductive current probe) . 10
4.5 Evaluation loads . 10
4.6 Human body model simulator . 10
4.7 HBM test equipment parasitic properties . 11
5 Stress test equipment qualification and routine verification . 11
5.1 Overview of required HBM tester evaluations . 11
5.2 Measurement procedures . 11
5.2.1 Reference pin pair determination . 11
5.2.2 Waveform capture with current probe . 12
5.2.3 Determination of waveform parameters . 12
5.2.4 High voltage discharge path test . 15
5.3 HBM tester qualification . 15
5.3.1 HBM ESD tester qualification requirements . 15
5.3.2 HBM tester qualification procedure . 15
5.4 Test fixture board qualification for socketed testers . 16
5.5 Routine waveform check requirements . 17
5.5.1 Standard routine waveform check description . 17
5.5.2 Waveform check frequency . 17
5.5.3 Alternate routine waveform capture procedure . 18
5.6 High voltage discharge path check . 18
5.6.1 Relay testers . 18
5.6.2 Non-relay testers . 18
5.7 Tester waveform records . 18
5.7.1 Tester and test fixture board qualification records . 18
5.7.2 Periodic waveform check records . 18

5.8 Safety. 19
5.8.1 Initial set-up . 19
5.8.2 Training . 19
5.8.3 Personnel safety . 19
6 Classification procedure . 19
6.1 Devices for classification . 19
6.2 Parametric and functional testing . 19
6.3 Device stressing . 19
6.4 Pin categorization . 20
6.4.1 General . 20
6.4.2 No connect pins . 20
6.4.3 Supply pins . 20
6.4.4 Non–supply pins . 21

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60749-26 © IEC:2013 – 3 –


6.5 Pin groupings . 21

6.5.1 Supply pin groups . 21

6.5.2 Shorted non-supply pin groups . 22

6.6 Pin stress combinations . 22

6.6.1 Pin stress combination categorisation . 22

6.6.2 Non-supply and supply to supply combinations (1, 2, … N) . 24

6.6.3 Non-supply to non-supply combinations . 25

6.7 Testing after stressing . 26

7 Failure criteria . 26


8 Component classification . 26
Annex A (informative) HBM test method flow chart . 27
Annex B (informative) HBM test equipment parasitic properties . 30
Annex C (informative) Example of testing a product using Table 2, Table 3, or Table 2
with a two-pin HBM tester . 34
Annex D (informative) Examples of coupled non-supply pin pairs . 40

Figure 1 – Simplified HBM simulator circuit with loads . 11
Figure 2 – Current waveform through shorting wires . 13
Figure 3 – Current waveform through a 500 Ω resistor . 14
Figure 4 – Peak current short circuit ringing waveform . 15
Figure B.1 – Diagram of trailing pulse measurement setup. 30
Figure B.2 – Positive stress at 4 000 V . 31
Figure B.3 – Negative stress at 4 000 V . 31
Figure B.4 – Illustration of measuring voltage before HBM pulse with a Zener diode or
a device . 32
Figure B.5 – Example of voltage rise before the HBM current pulse across a 9,4 V
Zener diode . 32
Figure C.1 – Example to demonstrate the idea of the partitioned test . 35

Table 1 – Waveform specification . 17
Table 2 – Preferred pin combinations sets . 23
Table 3 – Alternative pin combinations sets . 24
Table 4 – HBM ESD component classification levels . 26

Table C.1 – Product testing in accordance with Table 2 . 36
Table C.2 – Product testing in accordance with Table 3 . 37
Table C.3 – Alternative product testing in accordance with Table 2 . 38

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INTERNATIONAL ELECTROTECHNICAL COMMISSION

____________



SEMICONDUCTOR DEVICES –

MECHANICAL AND CLIMATIC TEST METHODS –



Part 26: Electrostatic discharge (ESD) sensitivity testing –

Human body model (HBM)



FOREWORD

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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.

International Standard IEC 60749-26 has been prepared by IEC technical committee 47:
Semiconductor devices in collaboration with technical committee 101.
This third edition cancels and replaces the second edition published in 2006. This edition
constitutes a technical revision. This standard is based upon ANSI/ESDA/JEDEC JS-001-
2010. It is used with permission of the copyright holders, ESD Association and JEDEC Solid
state Technology Association.
NOTE ANSI/ESDA/JEDEC JS-001 resulted from the merging of JESD22-A114F and ANSI/ESD STM5.1.
This edition includes the following significant technical changes with respect to the previous
edition:
a) descriptions of oscilloscope and current transducers have been refined and updated;
b) the HBM circuit schematic and description have been improved;

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60749-26 © IEC:2013 – 5 –


c) the description of stress test equipment qualification and verification has been completely

re-written;

d) qualification and verification of test fixture boards has been revised;


e) a new section on the determination of ringing in the current waveform has been added;

f) some alternate pin combinations have been included;

g) allowance for non-supply pins to stress to a limited number of supply pin groups

(associated non-supply pins) and allowance for non-supply to non-supply (i.e., I/O to I/O)

stress to be limited to a finite number of 2 pin pairs (coupled non-supply pin pairs);

h) explicit allowance for HBM stress using 2 pin HBM testers for die only shorted supply

groups.

The text of this standard is based on the following documents:
FDIS Report on voting
47/2160/FDIS 47/2167/RVD

Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts in the IEC 60749 series, published under the general title Semiconductor
devices – Mechanical and climatic test methods, can be found on the IEC website.
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.

IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct
understanding of its contents. Users should therefore print this document using a
colour printer.

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SEMICONDUCTOR DEVICES –

MECHANICAL AND CLIMATIC TEST METHODS –



Part 26: Electrostatic discharge (ESD) sensitivity testing –

Human body model (HBM)








1 Scope

This standard establishes the procedure for testing, evaluating, and classifying components
and microcircuits according to their susceptibility (sensitivity) to damage or degradation by
exposure to a defined human body model (HBM) electrostatic discharge (ESD).
The purpose (objective) of this standard is to establish a test method that will replicate HBM
failures and provide reliable, repeatable HBM ESD test results from tester to tester,
regardless of component type. Repeatable data will allow accurate classifications and
comparisons of HBM ESD sensitivity levels.
ESD testing of semiconductor devices is selected from this test method, the machine model
(MM) test method (see IEC 60749-27) or other ESD test methods in the IEC 60749 series.
The HBM and MM test methods produce similar but not identical results; unless otherwise
specified, this test method is the one selected.
2 Normative references
The following documents, in whole or in part, are normatively referenced in this document and
are indispensable for its application. For dated references, only the edition cited applies. For
undated references, the latest edition of the referenced document (including any
amendments) applies.
IEC 60749-27, Semiconductor devices – Mechanical and climatic test methods – Part 27:
Electrostatic discharge (ESD) sensitivity testing – Machine model (MM)
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.

3.1
associated non-supply pin
non-supply pin (typically an I/O pin) associated with a supply pin group
Note 1 to entry: A non-supply pin is considered to be associated with a supply pin group if either:
a) The current from the supply pin group (i.e., VDDIO) is required for the function of the electrical circuit(s) (I/O
driver) that connect (high/low impedance) to that non-supply pin.
b) A parasitic path exists between non-supply and supply pin group (e.g., open-drain type non-supply pin to a
VCC supply pin group that connects to a nearby N-well guard ring).
3.2
component
item such as a resistor, diode, transistor, integrated circuit or hybrid circuit

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60749-26 © IEC:2013 – 7 –


3.3

component failure

condition in which a tested component does not meet one or more specified static or dynamic

data sheet parameters


3.4

coupled non-supply pin pair

two pins that have an intended direct current path (such as a pass gate or resistors, such as

differential amplifier inputs, or low voltage differential signaling (LVDS) pins), including

analogue and digital differential pairs and other special function pairs (e.g., D+/D-,

XTALin/XTALout, RFin/RFout, TxP/TxN, RxP/RxN, CCP_DP/CCN_DN etc.)

3.5
data sheet parameters
static and dynamic component performance data supplied by the component manufacturer or
supplier
3.6
withstand voltage
highest voltage level that does not cause device failure
Note 1 to entry: The device passes all tested lower voltages (see failure Window).
3.7
failure window
intermediate range of stress voltages that can induce failure in a particular device type, when
the device type can pass some stress voltages both higher and lower than this range
Note 1 to entry: A component with a failure window may pass a 500 V test, fail a 1 000 V test and pass 2 000 V
test. The withstand voltage of this device is 500 V.
3.8
human body model electrostatic discharge
HBM ESD
ESD event meeting the waveform criteria specified in this standard, approximating the
discharge from the fingertip of a typical human being to a grounded device
3.9
HBM ESD tester
HBM simulator
equipment that applies an HBM ESD to a component
3.10

I
ps
peak current value determined by the current at time t on the linear extrapolation of the
max
exponential current decay curve, based on the current waveform data over a 40 nanosecond
period beginning at t
max
SEE: Figure 2 a).
3.11
I
psmax
highest current value measured including the overshoot or ringing components due to internal
test simulator RLC parasitics
SEE: Figure 2 a).
3.12
no connect pin
package interconnection that is not electrically connected to a die

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EXAMPLE: Pin, bump, ball interconnection.

Note 1 to entry: There are some pins which are labelled as no connect, which are actually connected to the die
and should not be classified as a no connect pin.


3.13

non-socketed tester

HBM simulator that makes contact to the device under test (DUT), pins (or balls, lands, bumps

or die pads) with test probes rather than placing the DUT in a socket


3.14

non-supply pins
all pins not categorized as supply pins or no connects
Note 1 to entry: This includes pins such as input, output, offset adjusts, compensation, clocks, controls, address,
data, Vref pins and VPP pins on EPROM memory. Most non-supply pins transmit or receive information such as
digital or analog signals, timing, clock signals, and voltage or current reference levels.
3.15
package plane
low impedance metal layer built into an IC package connecting a group of bumps or pins
(typically power or ground)
Note 1 to entry: There may be multiple package planes (sometimes referred to as islands) for each power and
ground group.
3.16
pre-pulse voltage
voltage occurring at the device under test (DUT) just prior to the generation of the HBM
current pulse
SEE: Clause C.2.
3.17
pulse generation circuit
dual polarity pulse source circuit network that produces a human body discharge current
waveform
Note 1 to entry: The circuit network includes a pulse generator with its test equipment internal path up to the
contact pad of the test fixture. This circuit is also referred to as dual polarity pulse source.
3.18
ringing
high frequency oscillation superimposed on a waveform

3.19
shorted non-supply pin
any non-supply pin (typically an I/O pin) that is metallically connected (typically < 3 Ω) on the
chip or within the package to another non-supply pin (or set of non-supply pins)
3.20
spurious current pulses
small HBM shaped pulses that follow the main current pulse, and are typically defined as a
percentage of I
psmax
3.21
socketed tester
an HBM simulator that makes contact to DUT pins (or balls, lands, bumps or die pads) using a
DUT socket mounted on a test fixture board

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60749-26 © IEC:2013 – 9 –


3.22

static parameters

parameters measured with the component in a non-operating condition


Note 1 to entry: These may include, but are not limited to, input leakage current, input breakdown voltage, output

high and low voltages, output drive current, and supply current.

3.23

step stress test hardening

ability of a component subjected to increasing ESD voltage stresses to withstand higher

stress levels than a similar component not previously stressed


EXAMPLE: A component may fail at 1 000 V if subjected to a single stress, but fail at 3 000 V if stressed
incrementally from 250 V.
3.24
supply pin
any pin that provides current to a circuit
Note 1 to entry: Supply pins typically transmit no information (such as digital or analogue signals, timing, clock
signals, and voltage or current reference levels). For the purpose of ESD testing, power and ground pins are
treated as supply pins.
3.25
test fixture board
specialized circuit board, with one or more component sockets, which connects the DUT(s) to
the HBM simulator
3.26
t
max
time when I is at its maximum value (I )
ps psmax
SEE: Figure 2a).
3.27
trailing current pulse
current pulse that occurs after the HBM current pulse has decayed
SEE: Clause C.1.
Note 1 to entry: A trailing current pulse is
...