IEC 63003:2015

Standard for the common test interface pin map configuration for high-density, single-tier electronics test requirements utilizing IEEE Std 1505™

IEC 63003:2015(E) the scope is the definition of a pin map utilizing the IEEE 1505 receiver fixture interface (RFI). The pin map defined within this standard shall apply to military and aerospace automatic test equipment (ATE) testing applications.

General Information

• Status: Published
• Publication Date: 13-Dec-2015
• ICS: 01 - GENERALITIES. TERMINOLOGY. STANDARDIZATION. DOCUMENTATION
• ICS: 25.040.01 - Industrial automation systems in general
• ICS: 29.060.10 - Wires
• Technical Committee: TC 91 - Electronics assembly technology
• Current Stage: PPUB - Publication issued
• Start Date: 31-Jan-2016
• Completion Date: 14-Dec-2015

Standards Content (Sample)

IEC 63003 ®
Edition 1.0 2015-12
™
IEEE Std 1505.1
INTERNATIONAL
STANDARD
colour
inside
Standard for the common test interface pin map configuration for high-density,
single-tier electronics test requirements utilizing IEEE Std 1505™

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IEC 63003 ®
Edition 1.0 2015-12
IEEE Std 1505.1™
INTERNATIONAL
STANDARD
colour
inside
Standard for the common test interface pin map configuration for high-density,

single-tier electronics test requirements utilizing IEEE Std 1505™

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 25.040 ISBN 978-2-8322-2941-5

IEEE Std 1505.1-2008
Contents
1. Overview . 1
1.1 Scope . 1
1.2 Purpose . 2
1.3 Statement of the problem . 2
2. Normative references . 3
3. Definitions, acronyms, and abbreviations . 4
3.1 Definitions . 4
3.2 Specification terms . 4
3.3 Acronyms and abbreviations . 4
4. Common test interface requirements . 8
4.1 Introduction . 8
4.2 CTI open system requirements . 8
4.3 CTI cost requirements. 9
4.4 Vertical integration test support requirements . 9
4.5 CTI configuration/interoperability requirements .10
4.6 Maintainability/end-user support requirements .10
4.7 Scaleable architecture requirements .10
4.8 Physical framework requirements .12
4.9 Reliability requirements.17
4.10 CTI connector footprint/parametric requirements .18
4.11 CTI pin map requirements .22
4.12 CTI pin map input/output configuration .33
Annex A (normative) Common test interface signal definitions for pin map.34
A.1 Analog instruments (AI) .34
A.2 Bus .36
A.3 Digital .37
A.4 Instrument control .37
A.5 Power loads .37
A.6 Power supplies .38
A.7 Sense and control, DCPS, and loads .38
A.8 Switch .39
A.9 System .40
Annex B (informative) Bibliography.159
Annex C (informative) IEEE List of Participants.162


vii
IEEE Std 1505.1-2008
IEEE Std 1505.1-2008
STANDARD FOR THE COMMON TEST INTERFACE PIN MAP
CONFIGURATION FOR HIGH-DENSITY, SINGLE-TIER
ELECTRONICS TEST REQUIREMENTS UTILIZING IEEE Std 1505™

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